Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
2000-11-28
2003-02-18
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C331S017000, C331S025000, C327S157000, C327S159000, C375S376000, C375S374000
Reexamination Certificate
active
06522204
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to phase-locked loops, and more particularly to a phase-locked loop using a voltage controlled crystal oscillator (VCXO) driven by logic in a programmable logic device (PLD) or application specific integrated circuit (ASIC) for ADSL frequency locking applications.
2. Description of the Prior Art
Phase-locked loops are commonly used in radio communications equipment, modem signal generators, and ADSL applications, among others. A phase-locked loop (PLL) consists generally of three parts: a reference frequency input portion, a loop filter portion, and a voltage-controlled oscillator (VCO) portion. The reference frequency portion includes a phase comparator and sometimes also includes a frequency divider. The phase comparator compares an output signal of the PLL with either a reference frequency or a reference frequency divided down, to produce an error signal. The error signal is filtered via the loop filter to produce a control signal that is applied to the VCO. During proper operation, the control signal drives the VCO in the proper direction so as to cause the error signal to be driven to zero or nearly zero. Modern PLL's are most commonly realized in the form of integrated circuits. As such, costs associated with modern PLL's have continued to increase and the performance characteristics associated with these modern PLL's have remained static in that these integrated circuits do not have the ability to adapt to a variety of reference frequencies and the like.
In view of the foregoing, a need exists for a cost effective PLL architecture that offers greater flexibility than that presently provided by packaged PLL's, for example, to adapt to a variety of reference frequencies, including reversion to center-frequency operation in the absence of a timing reference. Such a PLL would be particularly advantageous for ADSL frequency locking applications.
SUMMARY OF THE INVENTION
The present invention is directed to phase-locked loop for ADSL frequency locking applications. Specifically, a PLL is implemented for locking a voltage-controlled crystal oscillator to a low frequency reference clock. One application of the PLL includes locking an ADSL system clock to a network timing reference or to a voice PCM clock.
According to one embodiment, a PLL architecture uses a divider and phase comparator implemented along with other control logic in a small PLD and that is responsive to a low frequency reference, a charge pump filter, and a voltage-controlled crystal oscillator (VCXO) that is driven via the filtered output of the PLD. The low frequency reference is also called the network timing reference (NTR), although this input could also be another reference, such as the clock used for a PCM voice connection. The PLD produces a single tristated pulsed output. In closed-loop operation, this output consists of narrow logic high or low pulses in the vicinity of the positive edge of the NTR that keep the loop filter charged to the proper control voltage through a series resistor for frequency and phase lock. During most of each NTR cycle when pulses are not being generated, the PLD output is in a tristate condition, allowing the control voltage to maintain a nearly constant d-c voltage (since the input impedance of the VCXO is extremely high). In open-loop operation, the PLD output toggles continually between a logic high and low state at a duty cycle that maintains a nominal mid-range control voltage so that the VCXO will operate near its center frequency. Logic in the PLD selects closed-loop operation automatically when the NTR input is detected, and reverts to open-loop operation when NTR is not detected.
In one aspect of the invention, a PLL is implemented that offers considerable cost advantages over commercially available packaged PLL's suitable for use in clocked oscillator (CO) linecard designs.
In another aspect of the invention, a PLL is implemented that provides a great deal of flexibility for tuning the PLL to the jitter characteristics associated with a particular NTR or PCM clock source by making various digital timing parameters, as well as analog filter components easily accessible.
In yet another aspect of the invention, a PLL is implemented such that the PLL falls back to a midrange, rather than a minimum, operating frequency in the absence of a reference input to avoid the necessity of making a hardware selection that is dependent upon whether an NTR source is or is not connected.
In still another aspect of the invention, a PLL is implemented having control circuitry in digital form suitable for implementation in an ASIC.
In still another aspect of the invention, a PLL is implemented that provides for acceleration of the frequency capture time and the phase capture time over PLL's using conventional analog architectures.
In still another aspect of the invention, a PLL is implemented that has lock-in times compatible with the power-on train time of ADSL modems.
REFERENCES:
patent: 6223061 (2001-04-01), Dacus et al.
patent: 6369624 (2002-04-01), Wang et al.
Datasheet for “ICS73-01, PLL Building Block,” Integrated Circuit Systems, Inc., Apr. 11, 2000.
Brady III W. James
Hernandez Pedro P.
Kinkead Arnold
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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