Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-08-29
2004-07-27
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S147000, C375S376000, C331SDIG002
Reexamination Certificate
active
06768358
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of phase locked loop (PLL) frequency multipliers and, more particularly, to methods and apparatus for reducing the overhead associated with activating a PLL by providing an operative clock signal during the lock-time interval of the PLL.
BACKGROUND OF THE INVENTION
In many computing systems, digital devices, etc., the various clock signals required by a processor are often synchronized to a single reference clock signal and then distributed to the appropriate logic circuits, subsystems and components of the processor. The term processor refers, generally, to any apparatus that performs logic operations, computational tasks, and/or control functions. A processor may include one or more subsystems, components, and/or other processors. A processor will typically include various logic and/or digital components that operate using a clock signal to latch data, advance and/or sequence logic states, synchronize computations and logic operations, and/or provide other timing functions.
A cellular phone, for example, may include a processor having multiple subsystems or components such as a digital signal processor (DSP) operating at a high clock frequency in order to perform real-time, computationally intensive and often time-critical tasks, and a micro-controller (MCU) operating at a lower clock frequency to, for example, carry out various control functions, coordinate events, execute system software, etc. Moreover, the DSP and the MCU may each operate or have supporting components that operate at multiple clock frequencies. The clock frequency requirement at any given time may depend on the computational demands of the processor.
A frequency multiplier implemented by an analog or digital phase-locked loop (PLL) or delay-locked loop (DLL) is often employed to generate a high frequency clock signal and lock it in-phase with a reference clock. The high frequency clock signal may then be supplied to drive a logic circuit or component, provided to a clock distribution tree of a digital device, and/or otherwise distributed to a processor to meet the clocking requirements of the system. Thus, the clock frequency requirements of the various components of a processor may be supported from, and synchronized to, a single reference clock signal.
The term “provided” in the context of providing a clock signal describes a signal that is not disabled, bypassed, gated off, or otherwise prevented from being applied to, received by, and used for operation by the intended logic gates, digital components and/or circuitry, etc. In general, the term clocked component will be used herein to describe any of the above mentioned components. For instance, a clock signal may be provided to a bypass select, disable logic, clock distribution tree, etc., but is ultimately provided to a one or more low level components such as logic gates, flip-flops etc., requiring a clock as a logic level, a timing signal, a latch, etc. These low level components or collections of such low level components are referred to generally as clocked components.
FIG. 1
illustrates a block diagram of a conventional frequency multiplier
10
that generates an output clock signal from an input clock signal. Frequency multiplier
10
includes a PLL
12
that generates a high frequency output clock signal
32
and locks the signal in phase with input clock signal
30
.
The term clock signal, or simply clock, refers generally to any analog or digital periodic signal and, more particularly, a periodic signal used for or used to generate at least one timing signal or logic level for a logic component, digital circuit, or otherwise (i.e., a clocked component). A clock signal may be any of various waveforms including, but not limited to, sinusoids, square waves, pulse trains, etc. For example, a clock signal may be a signal that is ultimately used to advance the state of a processor, latch data, perform logic operations, etc. Signals such as swing sinusoids and signals from, for example, crystal oscillators from which one or more clock signals are formed and/or derived are additionally to be considered clock signals.
PLL
12
includes a phase comparator
22
, a loop filter
24
, a voltage controlled oscillator
26
and a divider
28
. Phase comparator
22
receives an input clock signal
30
and a feedback clock signal
34
and compares the phase of the two signals. Input clock signal
30
may be, for example, a system clock that provides a processor with a reference clock with which to synchronize the higher frequency clock signals distributed to the processor. Feedback signal
34
is related to the output clock signal
32
, having substantially the same phase as the output clock signal
32
and substantially the same frequency as the input clock signal
30
. Phase comparator
22
provides a phase error signal
40
proportional to the phase difference between the input clock signal
30
and the feedback clock signal
34
.
Loop filter
24
provides noise removal and smoothing to the phase error signal
40
. For example, loop filter
24
may include a low pass filter. In addition, loop filter
24
transforms the phase error signal
40
into a signal indicating a change in voltage required to reduce the magnitude of the phase error signal
40
. Voltage correction signal
42
, produced by the loop filter
24
, is provided to the VCO to correct for the phase difference between input clock signal
30
and feedback signal
34
.
A voltage controlled oscillator (VCO) typically provides a voltage to an oscillator which produces a signal having a frequency proportional to the provided voltage. As such, VCO
26
receives voltage correction signal
42
from loop filter
24
and adjusts a voltage supplied to the oscillator accordingly. The frequency of the output clock signal
32
is thereby adjusted to correct for the phase error detected by the phase comparator
22
(i.e., the output clock signal
32
is urged in-phase with the input clock signal
30
).
The output clock signal
32
is fed back to the phase comparator through divider
28
. Divider
28
may be, for example, a divide-by-n counter that divides the frequency of the output clock signal to provide feedback clock signal
34
for comparison with the input clock signal
30
. As such, the divider ratio n is typically chosen to match the multiplier ratio achieved by the VCO, thus providing the feedback clock signal having substantially the same frequency as the input clock signal and having substantially the same phase as the output clock signal.
Typically, there are various delays associated generating an output clock signal that is phase-locked to an input clock signal. In particular, there is an interval of time required for the phase-locked loop to converge (i.e., to lock the output clock signal in-phase with the input clock signal). The delay incurred while acquiring phase lock is often referred to as lock time.
FIG. 2
depicts a timing diagram illustrating delays often associated with generating an output clock signal that is phase-locked to an input clock signal by means of a frequency multiplier such as that illustrated in FIG.
1
. Plot
5
illustrates the frequency of an output clock signal (e.g., output clock signal
32
) as a function of time. In
FIG. 2
, it will be assumed that the PLL is not active at time t
0
. For example, no input clock signal is provided to the PLL, the VCO is not enabled, and no output clock signal is generated. In other words, time t
0
signifies the moment when it is first desired to supply an input clock to the frequency multiplier and power up the VCO, that is, when it is desired to activate the PLL.
A finite amount of time may be required before a stable input clock can be provided to the phase comparator of the PLL. This time is part of an interval, referred to as wake-up time, and indicated as interval
60
. Different PLL or DLL implementations may have other delays associated with the wake-up time. For instance, in the PLL of
FIG. 1
, there may be a delay associated with enabling the VCO to begin pro
Birk Palle
Soerensen Joern
Analog Devices Inc.
Nguyen Minh
Wolf Greenfield & Sacks P.C.
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