Phase-locked loop detecting circuit

Oscillators – Automatic frequency stabilization using a phase or frequency... – With reference oscillator or source

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331 25, 329122, H03L 700

Patent

active

045353069

ABSTRACT:
A circuit for detecting a proper locked state between the output of a phase-locked loop clock generating circuit and a timing component of a received composite signal containing both digital information and the timing component. An internal synchronization pulse signal is produced directly in response to the output of the phase-locked loop, and a frame synchronization sequence detection pulse signal is produced by detecting the occurrence of frame synchronization sequences in the composite signal. The internal synchronization pulse signal and the frame synchronization sequence detection pulse signal are compared to determine whether or not they are in time coincidence. If they are not, corresponding to an improperly locked state, a synchronization hunting controller controls the internal synchronization pulse generator to shift the phase of the internal synchronization pulse signal until time coincidence occurs. The output of the synchronization hunting controller is also used a lock detection signal. A frame synchronization signal is produced by delaying the output of the internal synchronization pulse generator.

REFERENCES:
patent: 3525945 (1976-08-01), Puente
patent: 4473801 (1984-09-01), Maurer et al.

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