Phase-locked loop delay line

Details Phase-locked loop delay line Phase-locked loop delay line

1988-06-03

1990-05-01

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307511, 307597, 307602, 307603, 328 55, 328155, H03K 5159, H03K 301

Patent

active

049221418

ABSTRACT:
A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase comparator. An error signal representative of phase error is developed and applied to vary the amount of delay until the phase error is eliminated. A precise delay referenced to the oscillator frequency is therefore achieved.

REFERENCES:
patent: 3206686 (1965-09-01), Goor
patent: 4277754 (1981-07-01), Minakuchi
patent: 4473752 (1984-09-01), Iwahashi et al.
patent: 4494021 (1985-01-01), Bell et al.
patent: 4495468 (1985-01-01), Richards et al.
patent: 4504749 (1985-03-01), Yoshida
patent: 4639680 (1987-01-01), Nelson
patent: 4641048 (1987-02-01), Pollock
patent: 4652778 (1987-03-01), Hosoya et al.
patent: 4710653 (1987-12-01), Yee
patent: 4737670 (1988-04-01), Chan
1988 IEEE International Solid-State Circuits Conference, Session XI: High Speed Logic, Mark G. Johnson, Edwin L. Hudson, p. 142.

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