Phase locked loop decoder

Details Phase locked loop decoder Phase locked loop decoder

1976-10-22

1978-04-18

Safourek, Benedict V.

Telegraphy

Systems

Line-clearing and circuit maintenance

331 1A, H03B 304

Patent

active

040852881

ABSTRACT:
A phase locked loop decoder for decoding digitally encoded data is disclosed in which each incoming data bit is synchronized to a clock frequency and a derived signal representative of the data cell width is varied in accordance with a derived phase error signal to compensate for bit shift and for data cell width variation which may be present in the incoming data. The phase error signal is a pulsed waveform having a leading edge synchronized with the occurrence of each data transition and a pulse width reprsentative of the phase error of the data with respect to the clock. The decoder will detect and decode data transitions having bit shifts of up to plus or minus 50 percent of the bit cell period.

REFERENCES:
patent: 3675129 (1972-07-01), Melvin
patent: 3805180 (1974-04-01), Widmer
patent: 3956710 (1976-05-01), Seitz et al.

Affiliated with

Also associated with

Rating

Phase locked loop decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop decoder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2148116