Phase locked loop control apparatus

Details Phase locked loop control apparatus Phase locked loop control apparatus

1995-05-18

1997-10-28

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327144, 327156, 331 11, 331 49, H03K 700, H03K 5159

Patent

active

056821123

ABSTRACT:
The phase locked loop (PLL) control apparatus includes a selector which selects input signals, for an active system and a standby system having a clock signal and a frame pulse signal synchronized with the clock signal, by means of a line switching signal. The phase difference between the frame pulses before and after the line switching is output by a frame pulse phase comparator. On the other hand, accompanying the line switching, a frequency divided clock output from a frequency divider is branched in a PLL control circuit which carries out the phase matching of the clocks. The branched clock is converted to pseudo clocks with duty factors larger than and smaller than 50% by a duty factor controller. A clock selector which selects one out of the frequency divided clock and the pseudo clock in response to the phase difference of the frame pulses is installed between a clock phase comparator and a low-pass filter of the PLL control circuit. The provision of a time gate which is linked with the line switching signal, it is also possible to terminate the phase matching after the lapse of a specified period of time. Furthermore, it is also possible to carry out a quicker and smoother phase matching by detecting the control voltage and setting the duty factor in response to the condition of the phase difference.

REFERENCES:
patent: 3795872 (1974-03-01), Napolitano et al.
patent: 4019143 (1977-04-01), Fallon et al.
patent: 4308619 (1981-12-01), Hughes
patent: 5184350 (1993-02-01), Dara
patent: 5355090 (1994-10-01), Pajowski et al.
patent: 5373254 (1994-12-01), Nakauchi et al.
patent: 5455840 (1995-10-01), Nakauchi et al.

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