Phase locked loop clock source provided with a plurality of freq

Details Phase locked loop clock source provided with a plurality of freq Phase locked loop clock source provided with a plurality of freq

1999-01-21

2000-11-28

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 25, 331 36C, 331 44, 331 74, 331158, 331177R, 331177V, 331179, H03B 532, H03L 718

Patent

active

061540951

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to an oscillator used as a clock source oscillation circuit for an information processor or a communication processor and capable of supplying a signal used as a reference for desired frequencies.
2. Description of Related Art
For use in information processors such as computers or in communication apparatuses, an oscillator in which a piezoelectric resonator such as a quartz resonator is used as an oscillation source has been used as a clock source or the like. Each of processing sections forming an information processor is supplied with a clock signal or the like having a suitable frequency on the basis of a signal supplied from such an oscillator. FIG. 18 shows an example of a conventional oscillator using a PLL circuit. This oscillator 90 is arranged so as to be able to select one of a plurality of frequencies predetermined to be output, and to output a signal having the selected frequency. The oscillator 90 has a quartz resonator 1, an oscillation signal output section 10 which oscillates the quartz resonator 1 to output an oscillation signal .phi.1 having a resonant frequency fc of the quartz resonator 1, a programmable divider (reference divider: RD) 15 which divides (by M) the oscillation signal .phi.1 to generate a reference signal .phi.2 having a frequency fr, a PLL circuit 20 which operates by being supplied with this reference signal .phi.2, a programmable divider (output divider: OD) 30 which divides (by X) a multiplied signal .phi.3 output from the PLL circuit 20 and having a frequency fp to generate an output signal .phi.4 having a frequency fo, and a buffer 35 which amplifies and outputs the output signal .phi.4. The PLL circuit 20 has a phase comparator 21 which compares the phase of reference signal .phi.2 supplied from the RD 15 and the phase of a signal fed back from a voltage controlled oscillator (VCO) 23, a low-pass filter (LPF) 22 which cuts off high frequency components of an output of the phase comparator 21 and supplies the cut output to the VCO 23, and the VCO 23 that oscillates so that the phases of the two signals input to the phase comparator 21 coincide with each other. Further, a feedback divider (FD) 24 is provided in a feedback circuit of the PLL circuit. The frequency of an output of the VCO 23 is divided (by N) by the FD 24 to be fed back to the phase comparator 21. Consequently, in the PLL circuit 20, multiplied signal .phi.3 formed by multiplying the signal input to the phase comparator 21 by N is output from the VCO 23.
Each of the dividers (frequency dividers) 15, 24, and 30 used in this oscillator 90 is a programmable divider capable of dividing the frequency of the input signal by a set frequency dividing number. Accordingly, in the oscillator 90 shown in FIG. 18, combinations of frequency dividing numbers M, N, and X for the frequencies to be output are previously set in a memory 95, and one of the combinations of the frequency dividing numbers M, N, and X stored in the memory 95 can be selected by a decoder 96 connected to an external input 94. For example, if the oscillator 90 uses a quartz resonator 1 having a resonant frequency fc of 20 MHz, it can select and output one of sixteen different frequencies according to a combination of four external terminals S0, S1, S2, and S3.
Use of a PLL oscillator using such a programmable divider has enabled one oscillator to cover a plurality of frequencies, thus making it possible to provide an oscillator capable of operating as stably as conventional quartz oscillators in the period before a restricted appointed limit of delivery. Recently, however, various requirements have been posed for reference oscillation sources and there has been a need to prepare various types of oscillators even if the above-described PLL oscillator is used. Further, the speed of development of information processors or communication apparatuses have been remarkably accelerated and, therefore, a need for manufacturing oscillators of new specifications or frequen

REFERENCES:
patent: 5451912 (1995-09-01), Torode
patent: 5608770 (1997-03-01), Noguchi et al.
patent: 5877657 (1999-03-01), Yoshinaka

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