Phase-locked loop clock signal generator

Details Phase-locked loop clock signal generator Phase-locked loop clock signal generator

1991-08-23

1993-06-22

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307603, 307606, 328 55, 328155, H03K 513, H03K 5159, H03K 301

Patent

active

052218635

ABSTRACT:
A variable delay circuit delays an input signal by an amount corresponding to a control signal. A signal delay amount of the variable delay circuit is detected by a delay amount detector circuit, and the detection signal is supplied to a charge pump circuit. In the charge pump circuit 12, a DC voltage according to a pulse width ratio of the input signal to an detection output from the delay amount detector circuit is generated and fed back to the variable delay circuit as the control signal. A predetermined DC voltage output from an initial voltage setting circuit is applied to a path of the control signal output from the charge pump circuit 12. An output voltage from the initial voltage setting circuit is set to be an approximate value of a value such that a desired delay amount is obtained in each of delay stages of the variable delay circuit, and the initial voltage setting circuit sets an initial value of the control signal.

REFERENCES:
patent: 4899071 (1990-02-01), Morales
patent: 4912433 (1990-03-01), Motegi et al.
patent: 4922141 (1990-05-01), Lofgren et al.
patent: 5054038 (1991-10-01), Hedberg
patent: 5059838 (1991-10-01), Motegi et al.
patent: 5562411 (1985-12-01), O'Rourke et al.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987; "Design of PLL-Based Clock Generator Circuits", pp. 255-261.

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