Phase locked loop clock extraction

Details Phase locked loop clock extraction Phase locked loop clock extraction

1999-03-11

2002-06-25

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Self-synchronizing signal

C375S327000, C375S376000

Reexamination Certificate

active

06411665

ABSTRACT:

BACKGROUND TO THE INVENTION
This invention relates to phased locked loop clock extraction and in particular, but not exclusively, to a sampling circuit for sampling clock signals relative to a data signal for determining phase quadrant values of the clock signal and to a frequency error detection circuit using the phase quadrant values.
It is known to utilize a phase locked loop as a means of clock recovery, as for example in the case of a data signal which is obtained by detecting an optical signal in an optical communications system, it being a general requirement at a receiver to synchronize a clock signal of the data signal before subsequent processing of the digital signal in the electrical domain. Typical data rates for such systems are in the range 1 to 10 GHz.
Phase locked loop circuits typically comprise a voltage controlled oscillator having an output which determines the clock frequency and an input voltage level set by a phase comparator and a loop filter. The phase comparator compares the phase of the clock signal with the data signal and, once the clock signal has initially been locked to the data signal, provides the necessary feedback via the loop filter to maintain the phase locked condition.
In order to provide improved response during initial acquisition of the phase lock condition, it also known to provide a frequency error detector which provides a frequency error signal representative of the difference in frequency between the clock frequency and the data rate, both phase error signals and frequency error signals being input to the loop filter during the acquisition phase.
It is known from EP-A-0557856 to discontinue input of the frequency error signal once the phase lock condition has been achieved in order to remove a source of jitter in the phase of the clock signal due to noise in the frequency error signal.
It is also known from Laurence DeVito, “A Versatile Clock Recovery Architecture and Monolithic Implementation”, from a compilation by IEEE Press titled “Monolithic Phase-Locked Loops and Clock Recovery Circuits” edited by Behzad Razavi, to provide the frequency error signal by first sampling a phase quadrant value of the clock signal by means of a sampling circuit in which a monostable multivibrator produces a strobe pulse for each transition of the data signal and obtains phase quadrant values by strobing a quadrature clock signal with the strobe pulse. A frequency error is determined to exist when the phase quadrant value changes in a manner consistent with the existence of frequency error. Specifically, if four phase quadrants of the clock signal are represented by values A, B, C and D such that the phase locked condition corresponds to the AD quadrant boundary, the frequency error detection circuit of DeVito detects a frequency error to exist when the measured phase quadrant value moves from B to C or from C to B, representing clock “too fast” and clock “too slow” conditions respectively.
A problem associated with the sampling circuit of DeVito is that it utilises a difference gate receiving both the signal pulse and a delayed signal pulse to generate the strobe signal and that therefore successful operation of this circuit is particularly dependent upon the accuracy of the value of delay. If the delay is too short, the strobe pulses become too narrow for triggering subsequent sampling latches. If on the other hand the delay is too long, the delayed pulse will not overlap the data pulse and no output strobe signal will be obtained. In practice, it may be difficult to achieve satisfactory stable operation due to difficulties in accurately setting the delay period when operating at frequencies in the GHz range.
It is also known from Mayo, U.S. Pat. No. 5,224,130, assigned to the assignee of the present application, to provide clock extraction using a phase locked loop. When the loop is out of lock, a frequency error signal is generated using a coincidence detector receiving both the data signal and the outputs of latch circuits in which the data signal is latched with the clock and quadrature clock signals. The frequency error signal is determined according to a predetermined algorithm based on values of the data signal obtained from the latch outputs.
There remains a need to provide an improved clock recovery system based upon phase detection and utilising frequency error detection during acquisition of the phase lock condition.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved sampling circuit for sampling a phase quadrant value of a clock signal.
It is a further object of the present invention to provide an improved frequency error detection circuit for a phase locked loop clock recovery system which is disabled when the phase locked condition is acquired.
It is a further object of the present invention to provide an improved frequency error detection algorithm for deciding when a change in phase quadrant value represents a frequency error in a phase locked looped circuit and which is tolerant to jitter in the data signal.
It is a further object of the present invention to provide a phase locked looped circuit having a frequency error detector which is immune to self-oscillation.
According to the present invention there is disclosed a method of sampling a clock signal in a clock recovery circuit at times corresponding to transition events between first and second values of a data signal from which the clock signal is recovered, the method comprising the steps of;
inputting the clock signal to a first latch switched by the data signal between a transparent state when the data signal has the first value and a hold state when the data signal has the second value;
inverting the data signal and inputting the clock signal to a second latch clocked by the inverted data signal between a transparent state when the data signal has the first value and a hold state when the data signal has the second value; and
multiplexing outputs of the first and second latches to select one of said outputs according to the value of the data signal to obtain a sampled output signal corresponding to the output of whichever one of the first and second latches is in the hold state.
Preferably the latches comprise transparent D type latches.
According to a further aspect of the present invention there is disclosed a method of operating a phase locked loop circuit to recover a clock signal from a received data signal in a clock recovery system, the method comprising the steps of;
determining a phase quadrant value representative of a quadrant of phase of the clock signal within which a transition event of the data signal occurs;
repeating the determining step for successive transition events to obtain a sequence of phase quadrant values;
determining the existence of a frequency error from changes in successive phase quadrant values in the sequence in accordance with a predetermined algorithm;
selectively generating a frequency error signal in accordance with said frequency error determination and inputting the frequency error signal to the phase locked loop circuit to change a frequency of oscillation of the circuit;
said algorithm being defined such that, if contiguous phase quadrant values are represented by A, B, C and D such that a transition between A and D corresponds to zero phase difference between the clock signal and data signal, a transition from A to B corresponds to the data being advanced relative to the clock signal, and a transition from C to D corresponds to the data being retarded relative to the clock signal, then
(a) a frequency error signal representative of the clock signal being too fast is generated only if successive quadrant values comprise one of:
(i) a change from B to C; and
(ii) a change from B to D; and
(b) a frequency error signal representative of the clock frequency being too slow is generated only if successive quadrant values comprise one of:
(i) a change from C to B; and
(ii) a change from C to A.
According to a further aspect of the present invention there is disclosed a method of operating a phas

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