Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Particular input circuit
Reexamination Certificate
2002-05-01
2003-04-29
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Particular input circuit
C377S075000, C377S080000, C377S081000
Reexamination Certificate
active
06556647
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits. More particularly, the present invention relates to an improved apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed programmable linear feedback shift register with a two stage pipeline in its feedback path.
BACKGROUND OF THE INVENTION
The use of linear feedback shift registers is well known in integrated circuit technology. Linear feedback shift registers may be used in a number of applications. For example, a linear feedback shift register may be used to implement a clock divider circuit. A clock divider circuit is used to divide a master clock signal to obtain a lower frequency clock signal.
In a phase locked loop (PLL) circuit, a clock divider circuit located within the feedback path needs to run at the frequency of the voltage controlled oscillator (VCO) in the PLL. The function of the PLL clock divider circuit in the feedback path is to divide the VCO frequency by a programmable value N (referred to as the “register value”). Division of the VCO frequency by the register value N provides an input to the phase detector within an analog core of the PLL. This causes a closed loop to be formed within the PLL. Clock divider circuits in the feedback path of a PLL are typically binary based counters or linear feedback shift register (LFSR) based counters.
High frequency PLL circuits have voltage controlled oscillators (VCO) that operate at very high frequencies. This, in turn, requires that the clock divider circuit in the feedback path of the PLL must also operate at very high frequencies. Prior art high frequency PLL circuits that have high frequency VCO output typically use custom designed binary counters or LFSR based counters in the feedback path that typically operate in the range of 250 MHz to 500 MHz. LFSR based counters operate at a relatively higher frequency compared to custom designed binary counters. To make prior art LFSR based counters to operate at frequencies greater than 500 MHz, the timing critical LFSR feedback path must have not more than one logic gate.
It would be desirable to have a high frequency PLL circuit having an LFSR based counter as a clock divider in its feedback path that would operate efficiently at frequencies greater than 500 MHz.
It would also be desirable to have a high frequency PLL circuit having an LFSR based counter as a clock divider in its feedback path with a shorter critical timing path than prior art LFSR based counters.
It would also be desirable to have a high frequency PLL circuit having an LFSR based counter as a clock divider in its feedback path having only one logic gate present in the critical timing path of the LFSR based counter.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed programmable linear feedback shift register (LFSR) with a two stage pipeline in its feedback path.
One advantageous embodiment of the present invention comprises (1) a linear feedback shift register (LFSR) based counter comprising a plurality of linear feedback shift register (LFSR) units and multiplexers, and (2) a plurality of “pre-load” flip flop (PLFF) circuits and multiplexers. Pre-calculated initial LFSR sequence values are stored in the “pre-load” flip flop circuits. The present invention generates a “load enable” signal to indicate when to load the pre-calculated initial LFSR sequence values into the LFSR units.
A feedback signal for the linear feedback shift register (LFSR) based counter is obtained by calculating an exclusive NOR value (XNOR) from the outputs of two of the LFSR units in the LFSR based counter. The feedback signal is obtained using a two stage pipeline in the feedback path of the LFSR based counter. The XNOR logic of the feedback path is implemented with NAND gates in each of the two pipeline stages. The feedback signal is used by a first LFSR unit (LFSR
0
) after three (3) successive input clock cycles from the falling edge of a “load enable” signal in order to compensate for the two stage pipeline delay introduced into the feedback path.
It is an object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register with a two stage pipeline in its feedback path that does not need to employ as many logic gates in a timing critical feedback path as prior art linear feedback shift registers.
It is another object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register with a two stage pipeline in its feedback path that is capable of operating at high frequencies.
It is also an object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register with a two stage pipeline in its feedback path that is capable of operating at a faster rate than prior art linear feedback shift registers.
It is another object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register with a two stage pipeline in its feedback path to have a scalable design that can implement an “any bit” clock divider having only two bits in its polynomial equation.
It is yet another object of the present invention to provide an apparatus and method for providing a phase locked loop clock divider circuit that utilizes a high speed linear feedback shift register with a two stage pipeline in its feedback path that is capable of generating desired frequencies for a clock divide signal by using non-timing critical “pre-load” flip flop circuits.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms “include” and “comprise” and derivatives thereof, mean inclusion without limitation, the term “or” is inclusive, meaning “and/or”; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term “controller,” “processor,” or “apparatus” means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain -words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.
REFERENCES:
patent: 6424691 (2002-07-01), Neravetl
Davis Munck, P.C.
National Semiconductor Corporation
Wambach Margaret R.
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