Phase-locked loop clock circuit for generation of audio sampling

Details Phase-locked loop clock circuit for generation of audio sampling Phase-locked loop clock circuit for generation of audio sampling

1996-07-03

1997-12-30

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331 60, 331 74, H03L 718

Patent

active

057035377

ABSTRACT:
A circuit with a phase-locked loop circuit which generates audio clock signals with zero ppm error from reference clock signals at a reference frequency is presented. The phase-locked loop (PLL) circuit has a first programmable divider circuit connected to the circuit input terminal, a first fixed divider circuit connected to the PLL output terminal and a second programmable divider circuit connected to the first fixed divider circuit, among other elements. The circuit also has several second fixed divider circuits, each second fixed divider circuit connected to the PLL output terminal, and a multiplexer selectively connecting the second fixed divider circuits to the circuit output terminal responsive to a programmable control signal. By properly selecting the integer divisors for the fixed and programmable divisors, the circuit can generate clock signals at any one of the audio sampling frequencies from a video clock signal.

REFERENCES:
patent: 5140284 (1992-08-01), Petersson et al.
patent: 5180992 (1993-01-01), Akiyama et al.
patent: 5184350 (1993-02-01), Dara
patent: 5278814 (1994-01-01), Deguchi et al.

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