Phase-locked loop clock

Pulse or digital communications – Spread spectrum – Direct sequence

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Details

331 1A, 375120, H03B 532

Patent

active

049724428

ABSTRACT:
There is provided a phase-locked loop clock circuit being operable in a tracking mode in response to a reference signal and in a sustaining mode in the absence of a reference signal. The circuit provides a relatively stable output clock signal in either of the two modes and permits smooth switchovers from one reference signal to another in a system with multiple reference signals. The circuit further provides a stable output clock if a reference signal temporarily fails.

REFERENCES:
patent: 3931585 (1976-01-01), Barker et al.
patent: 4151485 (1979-04-01), LaFratta
patent: 4466110 (1984-08-01), Kizaki et al.
patent: 4519071 (1985-05-01), Miller
patent: 4561101 (1985-12-01), Pinsard et al.
patent: 4724402 (1988-02-01), Ireland
patent: 4748644 (1988-05-01), Silver et al.

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