Phase locked loop ciruit for a liquid crystal display

Details Phase locked loop ciruit for a liquid crystal display Phase locked loop ciruit for a liquid crystal display

1996-11-26

1998-10-13

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 16, 331 36C, 331177V, 331DIG2, 327156, 327105, H03L 7099, H03L 710, H03L 718

Patent

active

058218181

ABSTRACT:
This single voltage controlled oscillator for a PLL circuit has two control loops: a low noise ration is maintained by a main loop; while a wide frequency capture range is ensured by a sub-loop controlled by a one-chip microcomputer. The main control loop is a low gain loop with a narrow capture range that compares the phase of the output of the PLL circuit with the phase of a horizontal synchronous video signal supplied to a LCD display. The sub-loop is a high gain loop with a broad frequency range that includes a processor that monitors the lock on the main loop. When the lock is broken, the processor increments or decrements the voltage supplied to this sub-loop in one or more steps until the lock is reestablished, and the PLL circuit is again operating within the narrow capture range of the low gain loop.

REFERENCES:
patent: 4131862 (1978-12-01), Black et al.
patent: 4213096 (1980-07-01), Daniel, Jr.
patent: 4513448 (1985-04-01), Maher
patent: 5036295 (1991-07-01), Kamitani
patent: 5124671 (1992-06-01), Srivastava
patent: 5254958 (1993-10-01), Flach et al.
patent: 5408196 (1995-04-01), Sempel et al.

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