Phase-locked loop circuits with current mode loop filters

Details Phase-locked loop circuits with current mode loop filters Phase-locked loop circuits with current mode loop filters

2007-11-20

2007-11-20

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000

Reexamination Certificate

active

11353832

ABSTRACT:
A phase-locked loop (PLL) includes a phase-frequency detector circuit configured to detect an error of an output clock signal in relation to a reference clock signal and to generate a charge pump control signal therefrom and a charge pump circuit configured to charge and discharge an output node thereof responsive to the charge pump control signal. The PLL further includes a current-mode loop filter circuit coupled to the output node of the charge pump circuit and configured to generate a filtered current from the current at the output node of the charge pump circuit, and a current-controlled oscillator configured to generate the output clock signal responsive to the filtered current. The current-mode loop filter circuit may be self-biased. For example, the current-mode loop filter circuit and the charge pump may be biased responsive to a common bias control signal generated by the current-mode loop filter circuit.

REFERENCES:
patent: 7148757 (2006-12-01), Chiu
Maneatis, et al., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” DAC 2003, Jun. 2-6, 2003, Anaheim, California, USA, pp. 688-690.
Lee et al., “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop,” IEEE Journal of Solid-State Circuits., Vo. 27, No. 12, Dec. 1992, pp. 1736-1756.
Cramomcix et al., “A Fully Integrated CMOS DCS-1800 Frequency Synthesizer,” IEEE Journal of Solid-State Circuits., vol. 33, No. 12, Dec. 1998, pp. 2054-2065.
Maxim et al., “A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless .18 μm CMOS PLL Based on a Sample-Reset Loop Filter,” IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov. 2001, pp. 1673-1683.
Maneatis et al., “Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,” IEEE Journal of Solid-State Circuits, vol. 38, No. 11, Nov. 2003, pp. 1795-1803.
Yang et al., “A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3 V/5 V Operation,” IEEE Journal of Solid-State Circuits, vol. 32, No. 4, Apr. 1997, pp. 582-586.
Maneatis, John G., “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Sidiropoulos, et al., “Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers,” 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 124-127.
Lee et al., “CMOS Continuous-Time Current-Mode Filters for High-Frequency Applications,” IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993, pp. 323-329.
Zele et al., “Low-Power CMOS Continuous-Time Filters,” IEEE Journal of Solid-State Circuits, vol. 31, No. 2, Feb. 1996, pp. 157-168.
Young et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1599-1607.

Affiliated with

Also associated with

Rating

Phase-locked loop circuits with current mode loop filters does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locked loop circuits with current mode loop filters, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop circuits with current mode loop filters will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3842042