Phase-locked loop circuitry for programmable logic devices

Details Phase-locked loop circuitry for programmable logic devices Phase-locked loop circuitry for programmable logic devices

1999-09-08

2001-04-17

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S159000, C326S093000

Reexamination Certificate

active

06218876

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic integrated circuit devices, and more particularly to phase-locked loop (“PLL”) circuitry for programmable logic devices.
It is well known to provide PLL circuitry on programmable logic devices for such purposes as counteracting clock signal propagation delay on the device, for enabling the device to convert from one clock signal frequency (e.g., an input clock signal frequency) to another different clock signal frequency (e.g., to be output by the device), etc. Some applications of programmable logic devices may require a PLL circuit to operate with frequencies outside a range that would be expected in most cases and for which a PLL circuit is readily designed. It would therefore be desirable to have PLL circuitry for programmable logic devices that can perform tasks conventionally requiring a PLL circuit to operate with very high and/or very low frequencies without the PLL circuitry that is provided having to support such a wide range of frequencies.
In view of the foregoing, it is an object of this invention to provide improved PLL circuitry for programmable logic devices.
It is a more particular object of this invention to provide PLL circuitry for programmable logic devices that extends the PLL capabilities of the devices without the necessity for extending the operating frequency range of any part of the PLL circuitry.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing a programmable logic device with two PLL circuits that are connectable in series. Part of the signal processing required to produce a desired frequency shift can be performed by the first of the two PLL circuits, and the remainder of the required signal processing can be produced by the second PLL circuit acting on the output of the first PLL circuit. Because each PLL circuit is only required to perform part of the required signal processing, neither PLL circuit has to operate with such extreme frequencies as would be required to produce some frequency shifts if all of the frequency shift had to be produced by a single PLL stage. Connecting two PLL circuits in series on the programmable logic device makes it easier to produce more different amounts of frequency shift without needing to use extreme frequencies in any part of the PLL circuitry. The series connection between the two PLL circuits can be programmable so that either or both of those circuits can be used separately if desired. If the two PLL circuits are not used in series, the programmable connection can make the input clock signal of the first PLL circuit the input clock signal of the second PLL circuit, rather than using the output signal of the first PLL circuit as the input signal of the second PLL circuit, as is done when the first and second circuits are operated in series.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.


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