Phase locked loop circuit with multiple combinations which each

Details Phase locked loop circuit with multiple combinations which each Phase locked loop circuit with multiple combinations which each

1999-03-12

2000-11-21

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

331 45, H03L 707, H03L 718, H03L 723

Patent

active

061508861

ABSTRACT:
A PLL circuit including multiple sets of phase locked loops, each of which has a phase comparator, a charge pump, a low pass filter, as oscillator, a clock generator and a frequency divider. The various oscillators of the multiple sets each have a different oscillation frequency. The clock generator generates a multiphase clock signal from a single phase clock signal generated by the oscillator. The PLL circuit generates multiple single phase clock signals and multiphase clock signals without need to tune the oscillation frequency of the VCOs over a wide range. The noise of the PLL is reduced since each VCO covers a smaller range of oscillation frequencies.

REFERENCES:
patent: 4833425 (1989-05-01), Culican, Sr. et al.
patent: 4904955 (1990-02-01), Ley
patent: 5270669 (1993-12-01), Jokura
patent: 5642039 (1997-06-01), Bradley et al.
patent: 5748044 (1998-05-01), Xue

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