Phase locked loop circuit with high stability having a reset sig

Details Phase locked loop circuit with high stability having a reset sig Phase locked loop circuit with high stability having a reset sig

1998-08-14

2000-05-23

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 331 8, 331 25, 331 57, 331173, 327142, 327156, 327157, 327158, 327159, H03L 706, H03L 708, H03L 7099, H03L 718

Patent

active

060669888

ABSTRACT:
A phase locked loop circuit includes a reset signal generating circuit for generating a reference clock signal and a reset signal from an input clock signal. A phase locked loop section generates an output clock signal based on the reference clock signal such that a phase of the output clock signal is locked in that of the reference clock signal. Also, the phase locked loop section is reset in response to the reset signal such that the phase of the output clock signal is locked in an initial value.

REFERENCES:
patent: 5495205 (1996-02-01), Parker et al.
Hata et al., "How to Use PLL-IC", published from Akiba syuppan on Feb. 10, 1986, pp. 21 to 24 and pp. 75 to 78.

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