Phase locked loop circuit with false locking detector and a lock

Details Phase locked loop circuit with false locking detector and a lock Phase locked loop circuit with false locking detector and a lock

1996-03-27

1997-09-23

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Search sweep of oscillator

331 1A, 331 8, 331 14, 331 17, 331 25, 331DIG2, 327157, 375376, H03L 7095, H03L 712

Patent

active

056709137

ABSTRACT:
Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order to avoid this, according to the invention, there is also included a false locking detector (FLD) to which is applied the incoming data signal (DS) and the recovered clock signal (RC) and the output of, which is added in an adder circuit (ADD) to that coming from the first loop, for producing voltage pulses when both signals are not at the same frequency, provoking a non-locked state. Only when the frequency is correct, does the false locking detector (FLD) not alter loop operation.

REFERENCES:
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patent: 4100503 (1978-07-01), Lindsey et al.
patent: 4213096 (1980-07-01), Daniel, Jr.
patent: 4297650 (1981-10-01), Shinmyo
patent: 4590602 (1986-05-01), Wolaver
patent: 5012494 (1991-04-01), Lai et al.
patent: 5485484 (1996-01-01), Williams et al.
"Monolithic Chip Retimes Data at 622 Mb/s" B. Lai et al, Microwaves and RF, vol.31, No.3, Mar. 1, 1992, pp. 202-205.
Patent Abstract of Japan, vol. 5, No. 91 (E-061) Jun. 13, 1981 & JP-A-56 035561 (Toshiba Corp.).
Patent Abstract of Japan, vol. 18, No. 425 (E-1590) Aug. 9, 1994 & JP-A-06 132818 (Fujitsu Ltd.).

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