Phase-locked loop circuit outputting clock signal having...

Details Phase-locked loop circuit outputting clock signal having... Phase-locked loop circuit outputting clock signal having...

2001-05-08

2003-10-21

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S005000, C327S148000, C331S025000, C331SDIG002, C375S376000

Reexamination Certificate

active

06636090

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-locked loop circuit for producing an output clock signal having a fixed phase difference with respect to its input clock signal.
2. Description of Related Art
Recently, the rate of the clock signal for an LSI (Large Scale Integrated circuit) has been increasing with the development of the micro-fabrication technique of the LSI. As a result, the margin is reduced of the phase difference between the clock signal of a system on which the LSI is mounted and the clock signal within the LSI. Thus, demand is increasing for using a phase-locked loop circuit that can compensate for the phase difference.
Likewise, the number of data signals input to the LSI is also increasing with the development of the micro-fabrication technique of the LSI. As a result, it becomes more difficult to establish synchronization between the data signals and the input clock signal because of the delay involved in the signal processing. Thus, demand is increasing for a circuit that can output a clock signal having a phase difference with respect to the input clock signal. Although such a circuit can be implemented by using a delay circuit, it is difficult for the circuit to compensate for an absolute value of the delay. In addition, it is easier to manage the phase of the clock signal than the delay considering the versatility of the phase-locked loop circuit.
Thus, a phase-locked loop circuit is required that can generate a compensable phase difference in order to produce a synchronous clock signal. Recently, such a circuit is implemented in the form of a DLL (Delay Locked Loop).
FIG. 5
is a block diagram showing a configuration of a conventional phase-locked loop circuit. In
FIG. 5
, the reference numeral
101
designates a PFD (phase frequency detector) having its first input terminal supplied with an input clock signal CLK, and its second input terminal supplied with a feedback clock signal FBCLK which will be described later;
102
designates a charge pump;
103
designates a lowpass filter; and
104
designates a VCO (Voltage controlled oscillator). The clock signal CLK
0
output from the VCO
104
is supplied to an internal circuit
105
of the LSI. The internal circuit
105
, on the other hand, supplies the feedback clock signal FBCLK to the second input terminal of the PFD
101
so as to control the output clock signal CLK
0
such that synchronization is established between the input clock signal CLK and the feedback clock signal FBCLK.
FIG. 6
is a block diagram showing the PFD
101
and the charge pump
102
constituting the phase-locked loop circuit. The PFD
101
converts the phase difference between the input clock signal CLK and the feedback clock signal FBCLK into a pulse width (time period).
FIG. 7
shows an example of the PFD
101
.
The PFD
101
as shown in
FIG. 7
has its input terminal PINP supplied with the input clock signal CLK, and its input terminal PINN supplied with the feedback clock signal FBCLK, and outputs a pulse with a width corresponding to the phase difference between the input clock signal CLK and the feedback clock signal FBCLK from an output terminal OUTP and an output terminal OUTN.
Next, the operation of the conventional PLL will be described.
FIGS. 8A
,
8
B and
8
C are timing charts illustrating the input and output signals of the PFD
101
as shown in FIG.
6
.
FIG. 8A
illustrates a case where the phase of the input clock signal CLK leads that of the feedback clock signal FBCLK. In this case, the PFD
101
outputs from its positive output terminal OUTP the output pulse with a width corresponding to the phase difference between the input clock signal CLK and the feedback clock signal FBCLK.
FIG. 8C
illustrates a case where the phase of the input clock signal CLK lags behind that of the feedback clock signal FBCLK. In this case, the PFD
101
outputs from its negative output terminal OUTN the output pulse with a width corresponding to the phase difference between the input clock signal CLK and the feedback clock signal FBCLK.
FIG. 8B
illustrates a case where the phase of the input clock signal CLK is synchronized with that of the feedback clock signal FBCLK, in which case the PFD
101
outputs two pulses with the same width. The two output pulses of the PFD
101
with the same width cause the output current of the charge pump
102
to be canceled to zero, thereby establishing the synchronization of the phase-locked loop circuit. In other words, the phase-locked loop circuit is brought into synchronization when the two output of the PFD
101
have the same pulse width.
In the foregoing operation, the width of a pulse P with a narrow width as illustrated in
FIGS. 8A-8C
is determined by a delay time of a delay circuit
111
of FIG.
7
. The delay circuit
111
is implemented by connecting an even number of inverters in cascade. The delay circuit
111
can be interposed at a position denoted by broken lines.
FIGS. 9A and 9B
are graphs obtained by plotting the average output current of the charge pump
102
against the phase difference between the input clock signal CLK and the feedback clock signal FBCLK of the circuit as shown in FIG.
6
:
FIG. 9A
illustrates the case where the pulse P with the narrow width is not output; and
FIG. 9B
illustrates the case where the pulse P is output. The zero-slope section D of
FIG. 9A
is called a dead band, in which the gain of the circuit is zero, thereby preventing the phase-locked loop circuit from operating. Such a characteristic is due to the delay of each component of the PFD
101
. The delay of these components can bring about such a case as the pulse corresponding to the phase difference between the input clock signal CLK and the feedback clock signal FBCLK is not produced even if there is such a phase difference. To avoid it, the dead band D must be eliminated by producing the pulse P with the narrow width.
The charge pump
102
connected after the PFD
101
converts the pulse width (time period) output from the PFD
101
into current or charges. For example, when a high level signal UP is supplied to its positive input terminal CINP, the charge pump
102
outputs a positive current, whereas when a high level signal DN is supplied to its negative input terminal, it outputs a negative current.
FIGS. 10A and 10B
each show an example of the charge pump
102
.
In the conventional phase-locked loop circuit with the foregoing configuration, it is difficult for the PFD
101
to detect the clock signal with a phase difference of 90 degrees. In addition, since the other components of the phase-locked loop circuit such as the charge pump
102
, the lowpass filter
103
and the VCO
104
do not have the function to detect the phase, they cannot detect the clock signal with the phase difference of 90 degrees. Although it might be detected by adding the frequency multiplication function to the phase-locked loop circuit using a frequency divider or the like, it is also difficult considering the delay of the internal circuit
105
of the LSI as shown in FIG.
5
. From the viewpoint of the phase difference compensation, it will be most preferable to establish 90-degree phase difference between the clock pulse and the feedback clock signal FBCLK supplied to the phase-locked loop circuit. Accordingly, an issue arises that it is necessary to construct a phase-locked loop circuit that can produce the output clock signal with the phase difference of 90 degrees with respect to the input clock signal by changing the configuration of the conventional phase-locked loop.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a phase-locked loop circuit capable of producing an output clock signal with a compensated phase difference with respect to the input clock signal.
According to a first aspect of the present invention, there is provided a phase-locked loop circuit comprising: a first phase detector for detecting a phase difference betw

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