Phase locked loop circuit including voltage controlled oscillato

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

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331 16, 331 1A, 331 36C, H03L 710

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active

060844809

ABSTRACT:
A PLL circuit of which pull-in time is reduced. The PLL circuit comprises a voltage controlled oscillator; a frequency divider which divides the frequency of the output signal from the voltage controlled oscillator; a phase detector which compares the phase of a standard signal and the frequency-divided signal and outputs an advanced phase signal and a delayed phase signal; a charge pump which charges and discharges a capacitor in a low pass filter, depending upon the advanced/delayed phase signals; a voltage supplier which supplies the control terminal of the voltage controlled oscillator with a voltage which corresponds to the desired voltage decided by the different output frequencies of the voltage controlled oscillator, when the output of the low pass filter is not virtually connected with the control terminal of the voltage controlled oscillator.

REFERENCES:
patent: 5021749 (1991-06-01), Kasai et al.
patent: 5335365 (1994-08-01), Ballantyne
patent: 5355098 (1994-10-01), Iwasaki
European Search Report dated Nov. 20, 1998.

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