Phase locked loop circuit including digital...

Details Phase locked loop circuit including digital... Phase locked loop circuit including digital...

2008-02-12

2009-10-20

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S045000, C331S057000, C331S179000

Reexamination Certificate

active

07605661

ABSTRACT:
A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks.

REFERENCES:
patent: 7424081 (2008-09-01), Suzuki
patent: 2001-510955 (2001-08-01), None
patent: 2002-100965 (2002-04-01), None
patent: 2005-191831 (2005-07-01), None

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