Phase locked loop circuit having main and auxiliary...

Details Phase locked loop circuit having main and auxiliary... Phase locked loop circuit having main and auxiliary...

2005-02-08

2005-02-08

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

06853222

ABSTRACT:
A PLL circuit including a generating means (3) for generating a plurality of reference signals (fR1to fR8) having mutually differing phases, a main frequency divider (30) dividing an output signal (fVCO) of a voltage-controlled oscillator (29) by a frequency-division ratio of N1, an auxiliary frequency divider (31) dividing an output (fV′) of the main frequency divider by a frequency-division ratio of N2, a distribution circuit (32) distributing an output (Q1a, Q2a, Q3a) of the auxiliary frequency divider as a plurality of feedback signals (fV1to fV8), and phase comparators (12to19) comparing the reference signals with the feedback signals to output error signals (ER1to ER8). Each of the main frequency divider and the auxiliary frequency divider is comprised of a variable frequency divider or a counter.

REFERENCES:
patent: 4550345 (1985-10-01), Terada et al.
patent: 5152005 (1992-09-01), Bickley
patent: 5162746 (1992-11-01), Ghoshal
patent: 6147561 (2000-11-01), Rhee et al.
patent: 07154252 (1995-06-01), None
patent: 08186488 (1996-07-01), None
patent: 10022824 (1998-01-01), None
patent: 10135822 (1998-05-01), None

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