Phase-locked loop circuit having correction for active...

Details Phase-locked loop circuit having correction for active... Phase-locked loop circuit having correction for active...

2005-08-22

2009-06-30

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C327S157000, C375S376000

Reexamination Certificate

active

07554412

ABSTRACT:
A phase locked loop (PLL) circuit automatically corrects the offset of the analog (especially active type) loop filter to improve the stability and precision of the locked clock or frequency signals. In addition to the general PLL circuit configuration having active type loop filter (30), the PLL circuit also has a frequency comparing circuit (42), a DAC controller (44) and a DAC (digital-to-analog converter) (46). In an offset measurement mode, the outputs of phase error detecting circuit (12, 14) and frequency error detecting circuit (18, 20) are cut, respectively, to establish locking in offset measurement locked loop (42, 44, 45, 30, 40). In this case, offset correction code (EDs) are identified and held. In normal mode, DAC controller (44) has offset correction code (ED) input to DAC (46), and DAC (46) sends offset correction signal (EAs) to loop filter (30).

REFERENCES:
patent: 4069462 (1978-01-01), Dunn
patent: 4404530 (1983-09-01), Stryer
patent: 4542351 (1985-09-01), Okada
patent: 5254955 (1993-10-01), Saeki et al.
patent: 5525935 (1996-06-01), Joo et al.
patent: 5546433 (1996-08-01), Tran et al.
patent: 6812797 (2004-11-01), De Veirman et al.

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