Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
2002-12-10
2004-10-26
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S011000, C331S025000, C327S156000, C345S204000
Reexamination Certificate
active
06809599
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase locked loop circuit having a function of automatically adjusting the free-running frequency of a voltage controlled oscillator.
2. Description of the Related Art
A phase locked loop (PLL) circuit including a phase comparator, a low-pass filter, and a voltage controlled oscillator (VCO), which are connected with each other into a loop, is used in a variety of applications. As an application, for use in displays, such as liquid crystal displays, organic electroluminescent (EL) displays, and plasma displays, such a PLL circuit is used for a display driving circuit of a display panel having pixels arranged into a dot matrix in order to generate a master clock based on a reference signal which is a horizontal synchronous signal or a vertical synchronous signal supplied from an external device.
A display driving circuit of such a display panel requires high accuracy and high stability master clock frequency. However, in the case where the frequency of the reference signal supplied to a PLL circuit from an external device greatly differs from the free-running frequency of a VCO in the PLL circuit, the output signal frequency of the VCO cannot be locked to the frequency of the reference signal unless the output signal frequency of the VCO is greatly shifted with respect to the free-running frequency of the VCO, thus impairing the stability of the output signal frequency of the VCO. This may not meet conditions requisite for the master clock of the display driving circuit. In a PLL circuit for generating a master clock of a display driving circuit, therefore, it is essential to adjust the free-running frequency of a VCO in the PLL circuit.
In the related art, a frequency counter for counting a master clock of a display driving circuit is used as an adjustment tool, which is connected to the display driving circuit in order to adjust the free-running frequency of a VCO. However, this mechanism has problems that such an adjustment tool is required and a time-consuming setting of connecting the adjustment tool to the display driving circuit is further required. Such a mechanism is also costly because the mechanism requires a checkout terminal for connecting the adjustment tool to the display driving circuit. In addition, the adjustment tool which is brought into contact with the checkout terminal causes a changing load of the master clock, leading to a measurement error.
The above-noted problems could be overcome by a PLL circuit having a function of automatically adjusting the free-running frequency of a VCO during operation of the PLL circuit. A PLL circuit having such a function is disclosed in Japanese Unexamined Patent Application Publication No. 2001-211072. In the PLL circuit disclosed in this publication, the output signal frequency of a VCO is converted into digital data by a frequency-to-data converter during operation of the PLL circuit, and the digital data is further converted into an analog signal by a digital-to-analog converter (DAC). The analog signal is added to a signal obtained by smoothing the output of a phase comparator by a low-pass filter, and the resulting signal is then input to the VCO as a frequency control signal, based on which the free-running frequency of the VCO is automatically adjusted.
In the PLL circuit disclosed in the publication, however, a high stability reference clock signal must be supplied to the frequency-to-data converter in order to activate the frequency-to-data converter. Thus, a circuit for generating such a reference clock signal is required, and, once the stability of the reference clock signal is reduced, the operation stability of the PLL circuit is also reduced.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a PLL circuit having an automatic adjustment for the free-running frequency of a VCO which does not require a circuit for generating a high stability reference clock signal, so that the operation stability of the PLL circuit can be maintained.
A phase locked loop circuit according to the present invention includes a voltage controlled oscillator having a control input terminal, a divide counter, a phase comparator, a counting unit, a data storing/updating unit, a digital-to-analog converter, a low-pass filter, and a combiner. The voltage controlled oscillator outputs a pulse signal having a frequency depending upon a frequency control signal supplied to the control input terminal. The divide counter divides the pulse signal received from the voltage controlled oscillator, and outputs the resulting pulse signal. The phase comparator receives as a first input signal a reference signal which is a pulse signal having a predetermined frequency supplied from an external unit, and receives as a second input signal the pulse signal output from the divide counter; and outputs a comparison signal. A period in which the comparison signal is at a predetermined level changes depending upon the phase difference between the first input signal and the second input signal. The counting unit counts the number of pulses of the pulse signal output from the voltage controlled oscillator in a period during which the comparison signal of the phase comparator is at the predetermined level. The data storing/updating unit updates stored digital data based on the count value of the counting unit. The digital-to-analog converter converts the digital data stored in the data storing/updating unit into an analog signal, and outputs the analog signal. The low-pass filter smoothes the comparison signal received from the phase comparator, and outputs the resulting signal. The combiner combines the output of the low-pass filter and the output of the digital-to-analog converter to generate a frequency control signal which is supplied to the control input terminal of the voltage controlled oscillator. The digital data is updated by the data storing/updating unit, thus allowing the free-running frequency of the voltage controlled oscillator to be automatically adjusted.
In a phase locked loop (PLL) circuit according to the present invention, therefore, the number of pulses of a pulse signal output from a voltage-controlled oscillator (VCO) in a period in which a comparison signal output from a phase comparator is at a predetermined level is counted, and digital data stored in a data storing/updating unit is updated based on the counted value. A digital-to-analog-converter (DAC) converts the digital data into an analog signal. A combiner combines the analog signal with a signal obtained by smoothing the comparison signal of the phase comparator by a low-pass filter to generate a frequency control signal of the VCO based on which the free-running frequency of the VCO is automatically adjusted. Since the PLL circuit of the present invention does not require a circuit for generating a high stability reference clock signal, the operation stability of the PLL circuit can be maintained. Thus, a PLL circuit having high accuracy and high stability is achieved.
REFERENCES:
patent: 3694766 (1972-09-01), Boelke
patent: 3883817 (1975-05-01), Cliff
patent: 4513448 (1985-04-01), Maher
patent: 4847569 (1989-07-01), Dudziak et al.
patent: 5254958 (1993-10-01), Flach et al.
patent: 6518845 (2003-02-01), Nakamichi
Frommer William S.
Frommer & Lawrence & Haug LLP
Mis David
Sony Corporation
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