Phase-locked-loop circuit having adjustable reference clock sign

Details Phase-locked-loop circuit having adjustable reference clock sign Phase-locked-loop circuit having adjustable reference clock sign

1993-06-22

1994-12-20

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 8, 331 25, H03L 7085, H03L 7093

Patent

active

053749049

ABSTRACT:
A phase synchronization circuit including a phase-locked-loop synchronizes a phase of a clock signal with a phase of a reference clock signal having a frequency desired by a user. The gates of an NMOS transistor and a PMOS transistors are connected in common to a resistor. The drain and the source of the NMOS transistor are both connected to a ground potential while the drain and the source of the PMOS transistor are both connected to a power source voltage. By changing a number of NMOS and PMOS transistors formed during a metallization process, the capacitance in a loop filter is easily changed.

REFERENCES:
patent: 4536720 (1985-08-01), Cranford, Jr. et al.
patent: 5053723 (1991-10-01), Schemmel
IEEE Journal of Solid-State Circuits, vol. sc-22, No. 2, Apr. 1987, Deog-Kyoon Jeong, et al., "Design of PLL-Based Clock Generation Circuits", pp. 255-261.

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