Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-03-27
2003-12-23
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S157000
Reexamination Certificate
active
06667640
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a phase locked loop (PLL) circuit and, more particularly, a PLL circuit having a relatively wide frequency oscillation range.
BACKGROUND INFORMATION
In recent years, efforts have been made to achieve a higher density of information recorded in a recording medium such as a digital data storage (DDS), a digital versatile disk (DVD), or a compact disk (CD), as well as in a recording device such as a hard disk drive (HDD), and to achieve a higher speed for reading/writing information. A recording/reproducing device has been presented for surely recording information at a writing speed enough for recording, and reading information at a reading speed higher than the writing speed. In a recording/reproducing device using a disk recording medium, a reading speed is greatly changed according to a head position in a radial direction of the disk. Thus, a PLL circuit for generating a clock signal for reading/writing must have a wide frequency oscillation range, and jitters of the PLL circuit are required to be reduced.
FIG. 1
is a schematic block diagram of a conventional PLL circuit
61
. The PLL circuit includes a phase comparator
62
, a charge pump
63
, a loop filter
64
, a voltage/current converter (referred to as V/I converter, hereinafter)
65
, a current controlled oscillator (CCO or ICO (referred to as ICO, hereinafter))
66
, and a frequency divider
67
.
The phase comparator
62
compares a phase of a reference signal fr with a phase of a frequency-divided signal supplied from the frequency divider
67
, and generates an up signal UP and a down signal DN each having a pulse width corresponding to a phase difference.
The charge pump
63
generates a charge pump output signal SCP having a current corresponding to the up signal UP and the down signal DN supplied from the phase comparator
62
.
The loop filter
64
is a low-pass filter (LPF) including a resistor and a capacitor, and removes a high-frequency component contained in the charge pump output signal SCP, and generates a filtered output signal SLF having a voltage.
The V/I converter
65
performs voltage/current conversion for the filtered output signal SLF, and generates a control signal SI having a current corresponding to a voltage of the filtered output signal SLF.
The ICO
66
generates an oscillation frequency signal fi having a frequency corresponding to a current of the control signal SI, supplies this oscillation frequency signal fi as a PLL oscillation signal to an external circuit (not shown), and the frequency divider
67
.
The frequency divider
67
divides a frequency of the oscillation frequency signal fi of the ICO
66
into a predetermined frequency-divided value (ratio of divided frequency), and generates a frequency-divided signal fp. The frequency-divided signal fp is fed back to the phase comparator
62
.
In place of the V/I converter
65
and the ICO
66
, a voltage controlled oscillator (VCO) may be used for generating an oscillation frequency signal fi having a frequency corresponding to a voltage of the filtered output signal SLF of the loop filter
64
.
In the PLL circuit
61
, if a frequency of the oscillation frequency signal fi is smaller than a desired locked frequency, a frequency of the frequency-divided signal fp becomes smaller than that of the reference signal fr, generating a phase difference between the frequency-divided signal fp and the reference signal fr. In this case, the phase comparator
62
generates an up signal UP having a pulse width larger than that of a down signal DN. In response to the up signal UP, the charge pump
63
charges the loop filter
64
for a period longer than a discharging period. Accordingly, a voltage of the filtered output signal SLF of the loop filter
64
increases. The V/I converter
65
generates a control signal SI having a current corresponding to the voltage of the filtered output signal SLF. Then, in response to the control signal SI, the ICO
66
increases a frequency of the oscillation frequency signal fi.
If a frequency of the oscillation frequency signal fi is larger than the desired locked frequency, a frequency of the frequency-divided signal fp becomes larger than that of the reference signal fr. In this case, the phase comparator
62
generates an up signal UP having a pulse width smaller than that of a down signal DN. In response to the up signal UP, the charge pump
63
charges the loop filter
64
for a period shorter than a discharging period. Accordingly, a voltage of the filtered output signal SLF of the loop filter
64
decreases. The V/I converter
65
generates a control signal SI by performing voltage/current conversion for the filtered output signal SLF. Then, in response to the control signal SI, the ICO
66
reduces a frequency of the oscillation frequency signal fi.
By repeating the above-mentioned operations, an oscillation frequency signal fi having a frequency matched (locked) with the desired frequency is output from the ICO
66
.
FIG. 2
is a schematic block diagram showing a conventional timing recovery PLL circuit (referred to as TR-PLL, hereinafter)
71
. The TR-PLL
71
includes, in addition to the components of the PLL circuit
61
of
FIG. 1
, a timing recovery control circuit (referred to as TR control circuit, hereinafter)
72
, a current controller
73
, and an ICO
74
. Components of
FIG. 2
similar to those of
FIG. 1
are denoted by similar reference numerals.
A V/I converter
65
a
receives a filtered output signal SLF from a loop filter
64
, and generates a control signal SI
1
for controlling an oscillation frequency of a first ICO
66
, and a control signal SI
3
for controlling an oscillation frequency of a second ICO
74
by performing voltage/current conversion for the filtered output signal SLF. A current of the control signal SI
1
is substantially equal to that of the control signal SI
3
.
The TR control circuit
72
receives a reading signal RD, and detects a phase difference of the reading signal RD with respect to an oscillation frequency signal ftr of the second ICO
74
by using the reading signal RD, thus generating a control signal STR. The reading signal RD is a signal read from a recording medium (not shown) according to the oscillation frequency signal ftr output from the second ICO
74
.
The current controller
73
includes a digital/analog converter (DAC). The current controller
73
corrects a current I
3
of the control signal SI
3
in accordance with the control signal STR output from the TR control circuit
72
, and generates a control signal SI
4
having a corrected current I
4
. For example, the TR control circuit
72
generates a control signal STR having a corrected value d corresponding to a phase difference of the reading signal RD. In response to the control signal STR, the current controller
73
corrects the current I
3
of the control signal SI
3
, and generates a control signal I
4
having a corrected current I
4
{I
4
=I
3
×d}.
The second ICO
74
generates an oscillation frequency signal ftr having a frequency corresponding to the corrected current I
4
of the control signal SI
4
from the current controller
73
. Then, data recorded in the recording medium is read in accordance with the oscillation frequency signal ftr.
Therefore, a frequency of the reading signal RD read from the recording medium is matched (locked) with that of the oscillation frequency signal ftr of the second ICO
74
, stabilizing a reading operation.
In the PLL circuit
61
of
FIG. 1
, an oscillation frequency of the ICO
66
corresponds to a current of the control signal SI of the V/I converter
65
(i.e., voltage of the filtered output signal SLF of the loop filter
64
). In other words, when a current of the control signal SI (voltage of the filtered output signal SLF) decreases, an oscillation frequency of the ICO becomes small. Thus, in the case where the current of the control signal SI (voltage of the filtered output signal SLF) is lowered to a predetermined value or lower, the ICO
66
is not oscillat
Callahan Timothy P.
Fujitsu Limited
Nguyen Linh
LandOfFree
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