Phase-locked loop circuit for use in synthesizer tuner and synth

Details Phase-locked loop circuit for use in synthesizer tuner and synth Phase-locked loop circuit for use in synthesizer tuner and synth

1978-04-13

1980-05-27

Griffin, Robert L.

Telecommunications

Transmitter and receiver at same station

With transmitter-receiver switching or interaction prevention

331 11, 331 1A, 455260, H04B 106

Patent

active

042052726

ABSTRACT:
A phase-locked loop (PLL) circuit and a synthesizer tuner incorporating the PLL circuit where a second DC control signal is applied to the PLL voltage controlled oscillator to reduce the phase error output signal from the PLL phase detector to near zero volts and thereby improve the performance of the voltage controlled oscillator and the S/N ratio of the tuner. Various circuits are disclosed for deriving the above second DC control signal. Further improvement in the S/N ratio is effected by switching in a narrow capture range for the PLL circuit when the desired signal is received and when the PLL phase detector output is operated near zero volts. Also when the station is changed, detuning is detected to switch in a broader capture range.

REFERENCES:
patent: 3375448 (1968-03-01), Newman et al.
patent: 3496473 (1970-02-01), Seppeler et al.
patent: 3660781 (1972-05-01), Tewksbury et al.
patent: 3703686 (1972-11-01), Hekimian
patent: 3753141 (1973-08-01), Van Elk et al.
patent: 3845393 (1974-10-01), Basset
patent: 3909735 (1975-09-01), Anderson et al.

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