Phase-locked loop circuit for reproducing clock signals synchron

Details Phase-locked loop circuit for reproducing clock signals synchron Phase-locked loop circuit for reproducing clock signals synchron

1996-11-18

1999-01-26

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

375376, H03L 708

Patent

active

058642480

ABSTRACT:
A phase-locked loop circuit comprising a received data counter for counting received clock signals reproduced according to sent data count values output from a transmitter, a subtracter for subtracting the output of the received data counter from an entered sent data count value, first and second attenuators for attenuating the output of the subtracter, an integrator for integrating the output of the second attenuator, an adder for adding the output of the first attenuator to the output of the integrator, a converter for converting the output of the adder into the corresponding voltage signal, and a voltage control oscillator that is controlled by the output of the converter and outputs a received clock signal to be supplied to the received data counter.

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patent: 5486792 (1996-01-01), Girardeau, Jr.
patent: 5488636 (1996-01-01), Yamada et al.
patent: 5525935 (1996-06-01), Joo et al.
patent: 5612981 (1997-03-01), Huizer
"A Survey of Digital Phase-Locked Loops", by William C. Lindsey and Chak Ming Chie, Proceedings of the IEEE, vol. 69, No. 4, Apr. 1981.
Electronic Information Society Technological Report, CAS 92-117 (CS92-106, DSP92-106) H. Uematsu, et al. (NTT Transfer Systems Research Laboratory), "Method of Clock Frequency Transmission Using SRTS in ATM Networks," Mar. 1993, pp. 55-62.
Garodnick et al., "Response of an All Digital Phase-Locked Loop" IEEE Transactions on Communications, vol. Com-22, No. 6, (1974), pp. 751-764.

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