Phase-locked loop circuit for reproducing a channel clock

Details Phase-locked loop circuit for reproducing a channel clock Phase-locked loop circuit for reproducing a channel clock

2006-01-31

2006-01-31

Patel, Gautam R. (Department: 2655)

Dynamic information storage or retrieval

Control of storage or retrieval operation by a control...

Control of information signal processing channel

C369S053200

Reexamination Certificate

active

06992958

ABSTRACT:
In PLL circuits for reproducing a channel clock in synchronism with data read from a disk-shaped recording medium driven for rotation, the frequency dividing ratio of frequency dividers provided in desired signal paths is made changeable according to the reproduced signal format of a CD reproduced signal or a DVD reproduced signal, for example. Although the frequency of the channel clock in synchronism with the reproduced signal differs in different signal formats, the above configuration makes it possible to reproduce the channel clock properly in accordance with a plurality of signal formats only by the operation of changing the frequency dividing ratio in a PLL circuit.

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