Phase-locked loop circuit for horizontal synchronization signal

Details Phase-locked loop circuit for horizontal synchronization signal Phase-locked loop circuit for horizontal synchronization signal

2000-08-22

2003-12-30

Miller, John (Department: 2614)

Television

Synchronization

Automatic phase or frequency control

C348S536000, C348S541000, C327S156000, C455S260000, C375S376000

Reexamination Certificate

active

06670995

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a phase-locked loop (PLL) circuit for a horizontal synchronization signal comprising a voltage-controlled oscillator (VCO) and a phase comparator. The phase comparator compares a phase of an input horizontal synchronization signal with a phase of a return (RET) signal to be fed back from the VCO and detects a phase difference value obtained by the result of the comparison and sent to the VCO. The RET signal is divided from a signal to be output from the VCO to a frequency capable of synchronizing with the horizontal synchronization signal. In accordance with the phase difference value, the PLL circuit locks both phases to maintain a synchronous condition. Specifically, the invention relates to the PLL circuit capable of avoiding any rapid change of the output frequency of the VCO even if the frequency level of the input horizontal synchronization signal is deteriorated to the level less than an appointed value, or disappears.
BACKGROUND OF THE INVENTION
In the recent years, a multiscan display applied to a wide frequency of the input synchronization signal is generally used. This brings about a necessity of the PLL circuit for the horizontal synchronization signal to cope with such requirements. Such PLL circuit is generally used for a television set or the like. However, an output circuit of the horizontal synchronization signal has a tendency to fail due to a rapid change of a frequency.
This is because, in the case where the frequency of pulses driving the output circuit of the horizontal synchronization signal changes rapidly, a high-voltage-proof transistor of a driver circuit breaks down. For example, there is a case that the frequency changes by about 10 percent in an instant, i.e., the case that the horizontal synchronization signal changes rapidly or disappears. In this event, the PLL circuit judges the disappearance as a large decrease of the frequency and tries to instantly cope with the change such that a rapid increase of the frequency should be executed and, as a result, the output circuit of the horizontal synchronization signal fails.
An existing PLL circuit of this type shown in
FIG. 1
, for example, connects serially a phase comparator
101
, a VCO
102
, and a dividing circuit
103
so as to form a loop. The phase comparator
101
compares the phases of an Hin (horizontal synchronized input) signal received from a terminal Hin with the RET signal from dividing circuit
103
and outputs a phase difference value to the VCO
102
from a charge pump circuit therein. To the input of the VCO
102
, an AFC filter (filter for Automatic Frequency Control)
104
also connects through a terminal F. By such a construction, the dividing circuit
103
divides the output frequency from the VCO
102
to the same frequency with the Hin signal from the terminal Hin. Following this, a phase synchronization between the Hin and the RET signals are maintained by a lock.
Referring to
FIG. 2
of a time chart and
FIG. 1
, description will be made about a case where the input of the Hin signal is disappeared.
Normally, both the Hin and the RET signals are locked at substantially equal phases. Accordingly, the edge timings of the waves in both signals are almost equal and a wave form sent from the charge pump, circuit of the phase comparator
101
is almost none, or an extrafine pulse in the terminal F.
On the other hand, in a case that there is no Hin signal in spite of existance of the RET signal, the comparator
101
follows the generation of the RET signal to supply a current continuously from the charge pump circuit to the AFC filter
104
. Accordingly, the VCO
102
judges it as a large decrease of the frequency and changes a performance so as to increase rapidly the output frequency. As a result, an output circuit for the horizontal synchronization signal would fail.
In order to resolve such problems, the following proposals are disclosed. For example, a switch supplied to an input side of a VCO is disclosed in Japanese Patent No. 2511858. In this prior art, the switch connects a reference voltage source to the VCO at a time when a comparator detects an Hin signal to disappear or any phase difference value to exceed a predetermined value. On the other hand, Japanese Unexamined Patent Applications (JP-A) Nos. H6-253169 and No. H6-339043 disclose a method of keeping a central mean voltage or an error margin voltage in a condition where no phase difference is occurred, and to supply the voltage at a time when any phase difference occurs.
However, even if such switch are supplied, the above-described disadvantageous phenomenon can not be erased at all during the time from a disappearance of the Hin signal or an occurrence of the phase difference exceeding the predetermined value until switching completion operated by the switch. A timing of the switching corresponds to an operation of the switch after the detection of any one of them. Accordingly, the above-described existing PLL circuit for the horizontal synchronization signal has a problem such as a possibility of failure of a circuit which outputs the horizontal synchronizing signal when a disappearance of the Hin signal or any occurrence of phase difference exceeding the predetermined value has occurred.
The reason is as follows. Even in a case where there is no input of the Hin signal or where the large delay is occurred despite of the supply of the RET signal, a comparator supplies a phase difference current continuously from the charge pump circuit to the AFC filter in response to the generation of the RET signal. This causes a rapid change of an output frequency from the VCO. Moreover, even such switch is installed, the above-mentioned problem can not be avoided in passing time after the occurrence of the above-described condition until a detection of the condition and a drive of the switch.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a phase-locked loop (PLL) circuit for the horizontal synchronization signal capable of avoiding a signal change for the VCO even when Hin signal is not supplied or a large delay has occurred despite the input of the RET signal.
A phase-locked loop (PLL) circuit for horizontal synchronization signal according to a present invention comprises a voltage-controlled oscillator (VCO), a phase comparator and a switch. The phase comparator compares a phase of an input horizontal synchronization signal with a phase of a return (RET) signal fed back from the VCO, and detects a phase difference value obtained by the above comparison and sent to the VCO. The RET signal from the VCO is divided into frequencies so as to be phase-comparable with a horizontal synchronization signal. In accordance with the phase difference value, the PLL circuit locks phases to maintain a synchronous condition of the phases. Specifically, in the output side of the comparator, a switch connects the detected phase difference value to the VCO during the horizontal synchronization signal is supplied.
As the above-mentioned composition gives the phase difference value to the VCO only during input of the horizontal synchronization signal, it is nothing that the VCO receives the phase difference value even if it brings about such abnormal condition of phase comparing as to input no horizontal synchronization signal. By this condition, the VCO has a judgment of no occurrence of the phase difference, and the oscillation of the VCO is continued as well as until then. As a result, it is capable of prevention of sudden change for a frequency of pulses to drive a circuit to output the horizontal synchronization signal.
Further provided with a first delay circuit, the horizontal synchronization signal is inputted and provided with a predetermined delay time thereto so as to be transmitted to the phase comparator. Accordingly, it is able to transmit the phase difference value with the delay time to the VCO. Moreover, provided with a second delay circuit to be supplied with the RET signal, the RET signal is provided with a predetermined delay time

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