Phase-locked loop circuit employing capacitance multiplication

Details Phase-locked loop circuit employing capacitance multiplication Phase-locked loop circuit employing capacitance multiplication

2011-05-03

2011-05-03

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S017000, C331S025000

Reexamination Certificate

active

07936222

ABSTRACT:
A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.

REFERENCES:
patent: 5942949 (1999-08-01), Wilson et al.
patent: 6344772 (2002-02-01), Larsson
patent: 6909329 (2005-06-01), Jasa et al.
patent: 1893331 (2007-01-01), None
English language translation of abstract of CN 1893331 (published Jan. 10, 2007).

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