Phase-locked loop circuit arrangement

Details Phase-locked loop circuit arrangement Phase-locked loop circuit arrangement

1982-04-02

1984-08-07

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

307269, 328 63, H04L 702

Patent

active

044647719

ABSTRACT:
The described invention relates to a phase-locked loop circuit arrangement for synchronizing an oscillator to a Non-Return-To-Zero data signal in which a transition from one potential level to another represents a data transition from one binary value to another.
A local clock signal is provided by means of a controllable oscillator and a phase comparator compares the phases of the data and clock singals with one another. The frequency of the oscillator is adjusted by means of a control signal in dependence upon an amount by which the phase of the data leads that of the clock signal and vice versa. In any cycle of the clock signal in which the phase of the clock signal leads that of the data and in which no data transition occurs the application of a control signal to the oscillator is inhibited.
The invention is particularly applicable to teletext receivers.

REFERENCES:
patent: 4180701 (1979-12-01), Louth et al.
patent: 4371975 (1983-02-01), Dugan

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