Industrial electric heating furnaces – Electron beam furnace device – Zone melting
Reexamination Certificate
2001-11-27
2003-10-28
Bocure, Tesfaldet (Department: 2631)
Industrial electric heating furnaces
Electron beam furnace device
Zone melting
C375S219000, C375S295000, C375S297000
Reexamination Certificate
active
06639933
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a phase-locked loop (hereinafter referred to PLL) for a transmission system included in a portable terminal for converting an intermediate frequency (IF) signal into a radio frequency (RF) signal mainly in the mobile communication and the portable terminal for the radio communication using the PLL.
A PLL system using a local signal frequency f
LO
to convert an input signal frequency f
IF
into an output signal frequency F
LO
-F
IF
is described in Chapter 10.3 of “PHASELOCK TECHNIQUES” (ISBN 0-471-04294-3) published by John Wiley & Sons and is shown in FIG.
10
. In
FIG. 10
, a phase comparator
18
compares a phase of an input signal frequency F
IF
with a phase of a reference signal frequency f
REF
and produces a signal proportional to a phase difference between the two input signals. The output signal of the phase comparator
18
is supplied to a low pass filter (LPF)
19
in which unnecessary harmonic components and noise are removed from the output signal and an output signal of the low pass filter is supplied to a VCO
20
. An output frequency f
RF
of the VCO
20
is supplied through a coupler
21
to a mixer
22
to be mixed with a local signal frequency F
LO
. An output frequency f
REF
of the mixer
22
is given by f
REF
=f
LO
−f
RF
. Since the output frequency f
REF
of the mixer
22
is equal to the frequency f
IF
when the PLL is in the lock state, the input signal frequency f
IF
is converted into the output frequency f
RF
=f
LO
−f
IF
of the VCO
20
.
As other examples of the PLL system for the frequency conversion, U.K. Patent No. GB 2 261 345 and U.S. Pat. No. 5,313,173 may be referred to. These references also use the same method as the fundamental principle of the PLL circuit.
In the above-described circuit, the output signal of the phase compactor is directly supplied to the low pass filter. Accordingly, in order to obtain a shorter settling time, it is necessary to broaden the frequency bandwidth of the PLL. On the other hand, however, when the frequency bandwidth is broadened, there is a problem that output noise is increased. Further, the circuit described in Chapter 10.3 of “PHASELOCK TECHNIQUES” (ISBN 0-471-14294-3) published by John Wiley & Sons is not considered to be used in a portable terminal.
FIG. 11
illustrates an example of circuit configuration for shortening the settling time when a voltage output type phase comparator is used. The PLL circuit includes the voltage output type phase comparator
23
, a voltage controlled oscillator (VCO)
24
, a coupler
25
, a mixer
26
, a reset switch
27
, a power supply
28
for use in shortening of a settling time and a low passfilter
29
. Usually, in the PLL circuit, the low pass filter, the VCO and the coupler are mounted externally to the PLL circuit. In this example, since the reset switch
27
and the power supply
28
are connected to the low pass filter
29
, the reset switch
27
and the power supply
28
are also mounted externally to the PLL circuit.
While the PLL operation is performed, the reset switch
27
is open (off state). When the PLL circuit is in the phase-locked state, the VCO
24
produces an output signal having a fixed frequency as a center frequency. A small radio communication apparatus such as a portable telephone mostly performs transmission in the time division manner. In this operation, a transmission period in which the PLL circuit is locked to perform transmission with the fixed center frequency and a transmission stop period in which the PLL operation is canceled after the transmission period are performed repeatedly. Further, there is a communication system in which the transmission frequency is changed at a certain period. In such a case, the PLL is locked to the same or different frequency after a predetermined period from cancellation of the locked state. For this end, a voltage for resetting the PLL operation is supplied to the VCO. The reset switch
27
is provided in order to apply the reset voltage. When the reset switch
27
is closed (on state), an input potential of the VCO
24
becomes 0 volts and the output frequency becomes a minimum oscillation frequency.
The voltage output type phase comparator
23
requires an operational amplifier
272
for converting a voltage output into a current output in order to supply a current to a low pass filter
271
. The operational amplifier
272
is necessarily required to adjust its operation characteristic and accordingly it is difficult to fabricate the operational amplifier into an IC chip. The negative DC voltage power supply
28
applies a negative bias voltage to an inverted input of the operational amplifier
272
to thereby shorten the settling time of the PLL. Since it is difficult to generate this negative voltage within the IC chip, the circuit of the negative voltage power supply
28
must be disposed outside the IC chip.
SUMMARY OF THE INVENTION
A phase-locked loop (PLL) circuit according to the present invention employs a phase comparator of current output type. By using the current output type phase comparator in the PLL circuit, it is not required to use an operational amplifier in a low pass filter (LPF). The PLL circuit including the current output type phase comparator, the LPF and a reset switch can be fabricated within an IC chip. Further, when a current source for supplying a current to the LPF is used together with the current output type phase comparator, a time from the start of control of the PLL to the locked state, that is, the settling time can be shortened. The PLL circuit according to the present invention realizes the compatibility of the short settling time or increased settling speed and low output noise without broadening of the band of the PLL.
Furthermore, the radio communication apparatus according to the present invention includes a transmission unit having the PLL circuit using the current output type phase comparator.
In the PLL circuit of the present invention, since an operational amplifier is not required in the LPF and the reset switch is fabricated in an IC chip, reliability and productivity of the PLL can be improved and the radio communication apparatus can be made small.
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D. Turner, “Phase-Locked Loop Phase Adjustment”,IBM Technical Disclosure Bulletin, vol. 15, No. 7, Dec. 1972, pp. 2080-2081.
Phaselock Techniques, Chapter 10.3, “Translation Loops”, pp. 204-207, date unknown, John Wiley & Sons, ISBN 0-471-04294-3.
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Furuya Tomio
Hildersley Julian
Kokubo Masaru
Watanabe Kazuo
Yamawaki Taizo
Antonelli Terry Stout & Kraus LLP
Bocure Tesfaldet
Hitachi. Ltd.
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