Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-01-18
2002-06-11
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S151000, C327S160000, C375S376000, C331SDIG002
Reexamination Certificate
active
06404249
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-locked loop circuit to be used for frequency modulation in digital equipment, and a frequency modulation method using the same. In particular, the present invention relates to a phase-locked loop circuit with a reduced chip size, and a frequency modulation method using the same.
2. Description of the Related Art
Generally, phase-locked loops (PLLS) are in use to make the phase of oscillator's signals coincide with and follow the phase of a reference signal. On this account, the signals output from the oscillator are constant in phase. In such PLL circuits, however, problems resulting from electromagnetic interference (EMI) have been pointed out recently.
In this view, there has been disclosed reduction of EMI by changing the oscillated frequency to obtain modulation frequency in a PLL circuit (Japanese Patent Application Laid-Open Nos. Hei 9-289527 and Hei 6-250755).
FIG. 1
is a block diagram showing a conventional PLL circuit.
A conventional PLL circuit comprises a phase and frequency detector (PFD)
52
, a charge pump (CP)
53
, a low-pass filter (LPF)
54
, and a voltage-controlled oscillator (VCO)
55
in series connection. Besides, a loop counter
51
for frequency-dividing signals output from the voltage-controlled oscillator
55
is connected to an input terminal of the phase and frequency detector
52
. A loop circuit is configured in this way. The phase and frequency detector
52
makes a comparison in phase between a reference frequency f
r
and the frequency of an output pulse of the loop counter
51
, and outputs the phase difference to the charge pump
53
. The charge pump
53
charges/discharges the capacitor provided in the low-pass filter
54
in accordance with a signal from the phase and frequency detector
52
. The low-pass filter
54
separates the input signal for transmission. The voltage-controlled oscillator
55
oscillates pulse signals in association with a change in the output voltage from the low-pass filter
54
.
The loop counter
51
is also connected with a ROM table
56
, and this ROM table
56
is connected with an up/down counter
57
. The ROM table
56
pre-stores dividing factors for use in frequency-dividing the output signal of the voltage-controlled oscillator
55
. The up/down counter
57
changes the addressing in the ROM table
56
for each output of the loop counter
51
.
In the conventional PLL circuit configured thus, the loop counter
51
outputs a pulse upon receiving a given number of pulse inputs that are output from the voltage-controlled oscillator
55
. Each output from the loop counter
51
changes the value of the up/down counter
57
, which in turn changes the address in the ROM table
56
. This results in the dividing factor in the loop counter
51
being changed for each output. Accordingly, the signals output from the PLL circuit also vary in frequency for each output.
FIG. 2
is a graphical representation on which the abscissa represents time and the ordinate represents oscillated frequency, schematically showing variation in the oscillated frequency of the output signal from the conventional PLL circuit. For example, in the case where the dividing factor output from the ROM table
56
repeats a given period of ascent and a given period of descent, the oscillated frequency varies, as shown in
FIG. 2
, to obtain a so-called triangular waveform. Such variation of the oscillated frequency suppresses the EMI problems.
Incidentally, configuration such as shown in
FIG. 1
is also described in U.S. Pat. No. 5,488,627.
However, conventional PLL circuits as described above require ROM tables, which produces a problem in that the circuits become greater in chip size or involve additional, dedicated chips. Besides, the modulation frequencies or ranges cannot be modified easily by reasons such that modifications to the modulation conditions inevitably require modifications to the ROM tables. Moreover, the ROM tables need to be provided with prescribed dividing factors in advance.
It is indeed possible to replace the ROM tables with RAMs; however, this brings about no solution to problems of increased chip size and the like.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a phase-locked loop circuit which is capable of reduction in chip size and easy modification to its modulation conditions, and a frequency modification method using the same.
According to one aspect of the present invention, a phase-locked loop circuit comprises an oscillator which outputs a pulse signal and a frequency divider for frequency-dividing the aforesaid pulse signal. The frequency divider has a dividing factor switching circuit which switches a dividing factor before a phase of the aforesaid pulse signal is locked to that of a reference clock signal.
In the present invention, the dividing factor is switched by the dividing factor switching circuit before the phase of the pulse signal is locked to that of the reference clock signal, allowing more gentle variation in the oscillated frequency as compared with the case where the dividing factor is not switched until the lock in phase. Accordingly, it is possible to increase or decrease the oscillated frequency before its saturation. This provides a so-called triangle waveform without the use of storage device such as a ROM.
According to another aspect of the present invention, a frequency modulation method comprises the step of switching a dividing factor before a phase of a pulse signal output from an oscillator is locked to that of a reference clock signal.
In the present invention, the dividing factor is switched before the phase of the pulse signal is locked to that of the reference clock signal, allowing more gentle variation in the oscillated frequency as compared with the case where the dividing factor is not switched until the lock in phase. Accordingly, it is possible to increase or decrease the oscillated frequency before its saturation. This provides a so-called triangle waveform without the use of storages such as a ROM.
The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters.
REFERENCES:
patent: 4916403 (1990-04-01), Sudoh et al.
patent: 5019907 (1991-05-01), Murakoshi et al.
patent: 5257294 (1993-10-01), Pinto et al.
patent: 5488627 (1996-01-01), Hardin et al.
patent: 5703537 (1997-12-01), Bland et al.
patent: 6044123 (2000-03-01), Takla
patent: 6-250755 (1994-09-01), None
patent: 7-235862 (1995-09-01), None
patent: 9-98152 (1997-04-01), None
patent: 9-289527 (1997-11-01), None
Hoekstra, Cornelis D., “Frequency Modulation of System Clocks for EMI Reduction”, Hewlett-Packard Journal, Aug. 1997, pp. 101-106.
Nguyen Minh
Tran Toan
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