Phase-locked-loop circuit and bit-detection arrangement comprisi

Details Phase-locked-loop circuit and bit-detection arrangement comprisi Phase-locked-loop circuit and bit-detection arrangement comprisi

1989-04-27

1991-11-19

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

329307, H03D 302

Patent

active

050671383

ABSTRACT:
A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.1, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E.sub.1, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from the relative positions (tf/T) and the phase values (F). The discrete-time oscillator (10) is controlled by a digital sequential filter (9) in such a way that the phase difference remains substantially zero.

REFERENCES:
patent: 4543531 (1985-09-01), Sugita et al.
patent: 4712223 (1987-12-01), Nelson
patent: 4807254 (1989-02-01), Otani
patent: 4807257 (1989-02-01), Schouhamer et al.

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