Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

2005-08-05

2008-10-21

Wang, Ted (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

C375S373000, C375S376000, C327S147000, C327S156000, C331S025000

Reexamination Certificate

active

07440518

ABSTRACT:
A PLL circuit comprises a controller (DRC) adjusting the frequency of frequency modulated signals (uDIV) provided by a frequency modulator (DIV) on the basis of signals provided by a linear range detector (LRD) so that the phase detector gets back into a linear range after a change in the frequency of said frequency modulated signals (uDIV) to a desired frequency. The lock time of the phase-locked loop circuit is improved without the requirement of complex circuitry.

REFERENCES:
patent: 4030045 (1977-06-01), Clark
patent: 6265362 (2001-07-01), Loderer et al.
patent: 6265902 (2001-07-01), Klemmer et al.
patent: 6441691 (2002-08-01), Jones et al.
patent: 6686803 (2004-02-01), Perrott et al.
patent: 7061288 (2006-06-01), Burgess
patent: 0 484 158 (1992-05-01), None
patent: 0 511 798 (1992-11-01), None
patent: 61-134125 (1986-06-01), None
patent: 2001-94415 (2001-04-01), None
Japanese Office Action dated Apr. 1, 2008, 7 pages.

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