Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

2007-11-27

2007-11-27

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S034000, C331S017000, C331S17700V, C331S17700V, C331S1170FE, C327S156000

Reexamination Certificate

active

11202266

ABSTRACT:
The present invention provides a PLL circuit containing a loop gain circuit capable of suppressing loop gain variation. This PLL circuit includes a counter that is driven by a voltage controlled oscillator within the PLL circuit, an accumulator (ACL) that accumulates the output of the counter, and a comparison operation circuit block that compares the count value of the ACL and the design value pre-stored in a register, and the loop gain of the PLL circuit is detected taking advantage of the fact that the ACL count value is inversely proportional to the loop gain. Based on the detection result, the loop gain is calibrated by correcting the loop gain with a charge pump current, etc. This allows the PLL circuit to maintain stable loop characteristics that will not affect the characteristics variation of each element constituting the PLL.

REFERENCES:
patent: 6130561 (2000-10-01), Dufour
patent: 6630868 (2003-10-01), Perrott et al.
patent: 2006/0220750 (2006-10-01), Akamine et al.
Hegazi, Ernad, et al., A 17-mW Transmitter and Frequency Synthesizer for 900-MHz GSM Fully Integrated in 0.35-μm CMOS, IEEE Journal of Solid-State Circuits, May 2003, vol. 38, No. 5, pp. 782-792.

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