Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

1986-07-24

1987-08-11

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

329 50, 329124, 375 85, H03D 318, H03D 324

Patent

active

046866892

ABSTRACT:
A phase-locked loop circuit receives an input signal that has a predetermined frequency during a succession of symbol intervals and of which the phase during a given symbol interval is related to the phase during a reference interval by the angle 2n.pi./N, where N is a positive integer and n is an integer in the range from 0 to (N-1), and generates a reference signal of which the phase has a desired relationship to the phase of the input signal during the reference interval. The circuit comprises a controllable oscillator that is responsive to a control signal to generate the reference signal, the frequency of the reference signal being equal to the predetermined frequency when the value of the control signal is zero. The circuit also comprises a demodulator for generating a first signal representative of the sine of the phase of the input signal relative to the reference signal and for generating a second signal representative of the cosine of the phase of the input signal relative to the reference signal, and a function generator for receiving the first and second signals and generating the control signal such that when the phase of the input signal relative to the reference signal is equal to 2n.pi./N plus the phase of the input signal relative to the reference signal during the reference interval, the value of the control signal is zero and the first derivative of the value of the control signal with respect to phase of the input signal relative to the reference signal is positive.

REFERENCES:
patent: 4027265 (1977-05-01), Kobayashi et al.
patent: 4484337 (1984-11-01), Leclert et al.
patent: 4555667 (1985-11-01), Cressey et al.

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