Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

2005-08-23

2005-08-23

Nguyen, Linh My (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S025000

Reexamination Certificate

active

06933790

ABSTRACT:
A PLL circuit for generating a clock signal synchronized with a first reference signal generated by superimposing a wobble signal on a land pre-pit signal or a second reference signal generated from a wobble signal. The PLL circuit enables reduction in circuit scale. When a DVD-R/RW is used as an optical disc, a first loop synchronizes the frequency of a wobble signal with the frequency of a divisional clock signal, which is generated from a recording clock signal of a voltage-controlled oscillator. Further, a second loop synchronizes the phase of the divisional clock signal with the phase of the LPP signal. When a DVD+R/RW is used as an optical disc, the first loop synchronizes the frequency of the divisional clock signal with the frequency of the wobble signal. Further, the second loop applies constant voltage to a control voltage input terminal of the voltage-controlled oscillator.

REFERENCES:
patent: 6456573 (2002-09-01), Ueki et al.
patent: 2002032962 (2002-01-01), None
Patent Abstracts of Japan, Publication No. 2002-230915, Publication Date Aug. 16, 2002.

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