Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

2002-04-16

2003-12-09

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S00100A

Reexamination Certificate

active

06661294

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-locked loop circuit used for circuits operated in synchronization with each other, and more particularly to a phase-locked loop circuit in which a frequency of an oscillation clock signal in a lock state can be stably maintained even at an occurrence time of an abnormal condition such as the loss of a reference input signal.
2. Description of Related Art
FIG. 11
is a block diagram of a first conventional phase-locked loop circuit. In
FIG. 11
,
51
indicates a tank circuit.
52
indicates a phase comparing unit.
53
indicates a low pass filter (LPF).
54
indicates a voltage controlled crystal oscillator (VCXO).
55
indicates a frequency divider. An output signal of the VCXO
54
is fed back to the phase comparing unit
52
through the frequency divider
55
so as to make a frequency of output signal of the VCXO
54
agree with an input clock signal received in the tank circuit
51
. Therefore, a conventional phase-locked loop (PLL) circuit is obtained.
Next, an operation of the first conventional phase-locked loop circuit will be described.
The tank circuit
51
is formed of a transformer, and an input clock signal is held in the tank circuit
51
for a predetermined time. Therefore, even though the input clock signal becomes unstable due to the occurrence of an abnormal condition in the input clock signal, a signal having a constant pulse width can be output from the tank circuit
51
for the predetermined time.
FIG. 12
is a block diagram of a second conventional phase-locked loop circuit. In
FIG. 12
,
61
indicates a phase comparing unit.
62
indicates a low pass filter (LPF).
63
indicates a voltage controlled crystal oscillator (VCXO)
64
indicates a frequency divider.
65
indicates an interruption detecting circuit for detecting the interruption of a reference clock signal.
66
indicates a control unit.
67
indicates a controlled voltage holding unit for holding and storing an output signal (denoting a controlled voltage for the VCXO
63
) of the LPF
62
.
68
indicates a selecting unit such as a selector.
In this conventional phase-locked loop circuit, a controlled voltage corresponding to a reference clock signal REF set in a normal condition is held and stored in the controlled voltage holding unit
67
, and the interruption of the reference clock signal can be detected in the interruption detecting circuit
65
. When the interruption of the reference clock signal is detected, the selection in the selecting unit
68
is changed by the control unit
66
, and the controlled voltage held and stored in the controlled voltage holding unit
67
is selected in the selecting unit
68
and is output to the VCXO
63
.
FIG. 13
is a block diagram of a third conventional phase-locked loop circuit disclosed in Published Unexamined Japanese Patent Application No. H7-273648 (1995). In
FIG. 13
,
71
indicates a phase comparing unit.
72
indicates a low pass filter (LPF).
73
indicates a voltage controlled oscillator (VCO).
74
indicates a counter for outputting a count value corresponding to a frequency division operation.
76
indicates a hold over circuit.
The configuration of the hold over circuit
76
is described.
77
indicates an interruption detecting unit.
78
indicates a control unit.
79
indicates a data holding unit.
80
indicates a comparing unit.
81
indicates a counter.
82
indicates a selecting unit.
83
indicates a pulse generating unit.
In the phase comparing unit
71
, an error signal Sc indicating a phase difference between an input clock signal Sa and a feed-back signal Sb is produced. In the interruption detecting unit
77
, the interruption of the input clock signal Sa is detected, and an interruption signal Sh is output. In the control unit
78
, a control signal Si is output according to the interruption signal Sh and a signal Sl. In the data holding unit
79
, the error signal Sc is held according to the control signal Si for a prescribed time, and a holding signal Sf denoting the error signal Sc is output. In the comparing unit
80
, the error signal Sc and the holding signal Sf are compared with each other, a signal Sj is output in cases where the level of the error signal Sc is higher than that of the holding signal Sf, and the signal Sl is output in cases where the level of the error signal Sc is lower than that of the holding signal Sf. In the counter
81
, a count value signal Sg indicating a count value is output according to the signal Sj and a signal Sk. In the selecting unit
82
, a selection signal SQ indicating the selection of either the error signal Sc or the holding signal Sf is output according to the control signal Si. In the pulse generating unit
83
, the feed-back signal Sb is output in an only case where a signal SB and the count value signal Sg are simultaneously set to a high level.
Next, an operation of the third conventional phase-locked loop circuit will be described below.
When the input clock signal Sa set in a normal condition is received in the phase comparing unit
71
, the error signal Sc output from the phase comparing unit
71
is selected in the selecting unit
82
, the error signal Sc is output from the selecting unit
82
as the selection signal SQ, the selection signal SQ is smoothed in the low pass filter
72
, an oscillation clock signal Se is output from the voltage controlled oscillator
73
, a count operation corresponding to a frequency division number is performed in the counter
74
according to the oscillation clock signal Se, and the signal SB is output from the counter
74
. Thereafter, a pulse of the feed-back signal Sb is output from the pulse generating unit
83
to the phase comparing unit
71
each time the signal SB and the count value signal Sg simultaneously set to a high level are received in the pulse generating unit
83
. Therefore, a phase-locked loop operation is performed in the third conventional phase-locked loop circuit.
When the interruption of the input clock signal Sa occurs due to the occurrence of an abnormal condition in the input clock signal Sa, the interruption of the input clock signal Sa is detected in the interruption detecting unit
77
, and the interruption signal Sh is output from the interruption detecting unit
77
to the control signal Si. Thereafter, the control signal Si corresponding to the interruption of the input clock signal Sa is output from the control unit
78
to both the selecting unit
82
and the data holding unit
79
. Because the error signal Sc obtained before the interruption of the input clock signal Sa is held in the data holding unit
79
, the holding signal Sf denoting the error signal Sc obtained before the interruption of the input clock signal Sa is output from the data holding unit
79
to both the comparing unit
80
and the selecting unit
82
under control of the control signal Si. In the selecting unit
82
, the holding signal Sf is selected under control of the control signal Si and is output as the selection signal SQ to the low pass filter
72
. In the comparing unit
80
, because the error signal Sc is interrupted, the error signal Sc cannot be received, but only the holding signal Sf is received. In this case, no signals Sj, Sk and Sl are generated in the comparing unit
80
, an operation of the counter
81
is stopped, and the count value signal Sg keeps the count value obtained before the interruption of the input clock signal Sa. Therefore, the same feed-back signal Sb as that in the normal condition is output from the pulse generating unit
83
to the phase comparing unit
71
.
However, in the first conventional phase-locked loop circuit shown in
FIG. 11
, because the tank circuit
51
has a coil of the transformer, an output condition in the tank circuit
51
is easily changed. Therefore, a problem has arisen that the first conventional phase-locked loop circuit is not stably operated due to the increase of jitters and wonders in an oscillation clock signal output from the voltage controlled crystal oscillator
54
.

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