Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

2002-07-08

2003-07-15

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S117000, C327S160000, C375S376000, C331SDIG002

Reexamination Certificate

active

06593787

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PLL, phase-locked loop, circuit. In particular, the present invention relates to a PLL circuit frequency synthesizer circuit.
2. Description of the Related Art
The conventional PLL circuit comprises a phase comparator, a low-pass filter, a voltage controlled oscillator, and a 1/N frequency divider. The 1/N frequency divider is comprised of at least one counter. The 1/N frequency divider is a circuit which divides a clock signal fvco output from the voltage controlled oscillator, and outputs a signal fp, with 1/N times the frequency of the clock signal fvco. The phase comparator is a circuit that compares a phase of a reference clock signal and a phase of the clock signal fp, output from the frequency divider, and outputs a signal based on the result of the comparison. The low-pass filter is a circuit that removes high frequency noise output from the phase comparator. The voltage controlled oscillator outputs the clock signal fvco having a frequency related to the output voltage output from the low-pass filter.
The conventional 1/N frequency divider only divides the frequency of the clock signal fvco output from the voltage controlled oscillator. The 1/N frequency divider counts the pulse of the clock signal N times, from the time at which the clock signal fp falls. The 1/N frequency divider then lowers the clock signal fp. The voltage controlled oscillator outputs a higher frequency of the clock signal fvco responding to the phase difference between the clock signal fp and the reference clock signal, if the fall of the clock signal fp is delayed compared to the fall of the reference clock signal.
Here, if the fall of the clock signal fp output from the 1/N frequency divider is delayed compared to the fall of the reference clock signal, the 1/N frequency divider does not count the pulse of the clock signal fvco from the time of the fall of the reference clock signal. Instead, the 1/N frequency divider counts the pulse of the clock signal fvco from the time of the fall of the clock signal fp, which is later than the fall of the reference clock signal. The 1/N frequency divider then lowers the clock signal fp again. Next, the frequency of the clock signal fvco is newly determined, based on the difference of the time of the subsequent fall of the clock signal fp and the subsequent fall of the reference clock signal.
Here, the subsequent fall of the clock signal fp is related to the previous fall of the clock signal fp. Because the clock signal fp falls again after counting the pulse of the clock signal fvco N times from the time of the previous fall of the clock signal fp, the subsequent fall of the clock signal fp is related to the previous fall of the clock signal fp.
Furthermore, the clock signal fvco, which is generated based on the subsequent fall of the reference clock signal and the subsequent fall of the clock signal fp, is also related to the previous fall of the clock signal fp.
Therefore, if the previous fall of the clock signal is delayed more than the previous fall of the reference clock signal, the clock signal falls again. This fall occurs after the clock signal fvco is counted N times from the previous fall of the clock signal fp, and not from the previous fall of the reference clock signal. Thus, the subsequent fall of the reference clock signal and the subsequent fall of the clock signal fp do not match without using a clock signal fvco having an extremely high frequency. Therefore, there is a problem because it takes time to match both the frequency and phase of the reference clock signal and the clock signal fp.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a phase-locked loop circuit which overcomes the above issues in the related art.
The phase-locked loop circuit of the present invention is provided with first and second phase comparators. The first phase comparator compares a phase of a first frequency divided signal, generated by dividing the frequency of a reference clock signal, and a second frequency divided signal output by a first frequency dividing circuit. The second phase comparator compares the phase of the first frequency divided signal, after it has been inverted, and a third frequency divided signal output by a second frequency dividing circuit. A low-pass filter outputs a signal determined by output signals of the first and second phase comparators, and couples it to a voltage controlled oscillator which generates an oscillator pulse signal having a frequency determined by the output of the low-pass filter.
The first frequency dividing circuit includes a first N-ary counter and a first latch circuit coupled to an output of the first N-ary counter, and the second frequency dividing circuit includes a second N-ary counter and a second latch circuit coupled to an output of the second N-ary counter. Inputs of the first and second N-ary counters receive the oscillator pulse signal generated by the voltage controlled oscillator.
The first latch circuit inputs the second frequency divided signal to the first phase comparator, and the second latch circuit inputs the third frequency divided signal to the second phase comparator. When a change in the oscillator pulse signal follows a change in the first frequency divided signal, a reset signal circuit applies first and second set signals to set input pins of the first and second latch circuits respectively and to reset terminals of the first and second N-ary counter respectively. The first set signal initiates, at the output of the first latch circuit, generation of the second frequency dividing signal at a first level. The second set signal initiates, at the output of the second latch circuit, generation of the third frequency dividing signal at a second level. The first and second set signals further initiate counting by the first and second N-ary counters of a predetermined number of pulses of the oscillator pulse signal. The first and second N-ary counters input reset signals to reset input pins of the first and second latch circuits respectively when the predetermined number of pulses of the oscillator pulse signal have been counted. The second frequency dividing signal then changes from the first level to a second level, and the third frequency dividing changes from the second level to the first level.
This summary of the invention does not necessarily describe all necessary features. The invention may also be a sub-combination of these described features.


REFERENCES:
patent: 4166979 (1979-09-01), Waggener
patent: 5304954 (1994-04-01), Saito et al.
patent: 5389897 (1995-02-01), Gebara
patent: 5953386 (1999-09-01), Anderson
patent: 5977806 (1999-11-01), Kikuchi
patent: 6066988 (2000-05-01), Igura
patent: 6225840 (2001-05-01), Ishimi
patent: 6281727 (2001-08-01), Hattori

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