Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

2001-10-12

2003-03-25

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S03600C, C331S175000, C331S17700V

Reexamination Certificate

active

06538519

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to phase-locked loop circuits and in particular phase-locked loop circuits with split loop filters.
PRIOR ART
Phase-locked loops (PLLs) which use feedback to maintain the frequency/phase of a signal in specific relationship with a reference signal are well known and commonly used in frequency synthesizers along with other applications. Frequency synthesizers are commonly used in radio receivers and transmitters to accurately generate a signal of any given frequency within a range of frequencies. A large volume application of frequency synthesizers at the date of this application is as local oscillators in cellphones.
The basic components of a phase-locked loop are shown in
FIG. 1
where a voltage controlled oscillator (VCO)
1
produces the desired output signal &ugr;
o
. This output signal is fed to a phase detector
2
through an integer divider
3
(which in use is used to select the output frequency). The second input of the phase detector
2
is a reference frequency signal &ugr;
ref
and any difference in frequency between the output frequency and the reference frequency manifests as a phase difference and generates an error signal at the output of phase detector
2
. The error signal controls the frequency of VCO
1
by controlling the capacitance of a varactor in the oscillator tuning circuit, but to ensure the feedback loop so formed is stable, the error signal is passed through a loop filter
4
. The loop filter
4
shapes the frequency response of the PLL in accordance with traditional control system theory.
PLLs are implemented using large scale integrated circuits and it is highly desirable for all components of the PLL to be implemented in a single chip.
In wireless applications, phase-locked loop frequency synthesizers require very good phase noise performance in order to obtain a good signal-to-noise ratio for the desired signals even in the presence of very large nearby unwanted signals. Inside the frequency synthesizer, the thermal noise generated by the charge pump and by the resistors in the loop filter will modulate the voltage-controlled oscillator
2
and degrade the phase noise performance. In order to reduce the thermal noise, the loop filter requires high value capacitors that are too large to be put on the chip. As a result, off-chip capacitors need to be used and thus the product size and cost are inevitably increased.
In U.S. Pat. No. 5,384,502 a split loop filter (also referred to as dual-loop filter) has been proposed as an effective solution to reduce the size of these capacitors, in which one branch of the loop filter includes an integrator, the other branch a low-pass filter, and a voltage adder is employed to combine the signals from the two branches to form the error signal which controls the VCO. However, this solution has the disadvantage of requiring a low-noise wide-dynamic-range voltage adder. This either contributes excess noise or consumes excess power and chip area.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a phase-locked filter having a split loop filter which does not require a low-noise wide-dynamic-range voltage adder.
It is a further object of the present invention to provide a phase-locked loop employing a split loop filter which allows the value of the filter capacitors to be minimized.
The invention consists in a phase-locked loop wherein the signal of a voltage controlled oscillator frequency is locked to a reference signal, and wherein said oscillator frequency is controlled by the output of a phase comparison circuit through a split loop filter including an integrator filter generating a first error voltage with respect to the reference and oscillator signals, and a low pass filter generating a second error voltage with respect to the reference and oscillator signals. The improvement comprises providing at least two varactors in parallel to control the frequency of said voltage controlled oscillator, and connecting the first error voltage to at least one varactor and the second error voltage to the remaining varactor.
In this invention the split loop filter is modified such that the output of the integrator and that of the low-pass filter are used to separately control two parallel varactors. As a result, the summing is inherently done in the capacitance domain, and a voltage adder is not needed. Moreover, the two paths in the loop filter become completely separated and can be independently optimized.


REFERENCES:
patent: 5384502 (1995-01-01), Volk
patent: 5821818 (1998-10-01), Idei et al.
Mijuskovic, et al., Cell-Based Fully Integrated CMOS Frequency Synthesizers, Mar., 1994, pp. 271-279, vol. 29, No. 3, IEEE Journal of Solid-State Circuits.
Craninckx, et al., A Fully Integrated CMOS DCS-1800 Frequency Synthesizer, Dec. 1998, pp. 2054-2065, vol. 33, No. 12, IEEE Journal of Solid-State Circuits.

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