Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

2000-03-17

2002-09-24

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S160000, C327S117000, C327S162000, C375S376000, C331SDIG002

Reexamination Certificate

active

06456132

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit. In particular, the present invention relates to a PLL circuit frequency synthesizer circuit.
2. Description of the Related Art
The conventional PLL circuit comprises a phase comparator, a low-pass filter, a voltage controlled oscillator, and a 1/N frequency divider. The 1/N frequency divider is comprised of at least one counter. The 1/N frequency divider is a circuit which divides a clock signal fvco output from the voltage controlled oscillator, and outputs a signal fp with 1/N times the frequency of the clock signal fvco. The phase comparator is a circuit that compares a phase of a reference clock signal and a phase of the clock signal fp, output from the frequency divider, and outputs a signal based on the result of the comparison. The low-pass filter is a circuit that removes high frequency noise output from the phase comparator. The voltage controlled oscillator outputs the clock signal fvco having a frequency related to the output voltage output from the low-pass filter.
The conventional 1/N frequency divider only divides the frequency of the clock signal fvco output from the voltage controlled oscillator. The 1/N frequency divider counts the pulse of the clock signal N times, from the time at which the clock signal fp falls. The 1/N frequency divider then lowers the clock signal fp. The voltage controlled oscillator outputs a higher frequency of the clock signal fvco responding to the phase difference between the clock signal fp and the reference clock signal, if the fall of the clock signal fp is delayed compared to the fall of the reference clock signal.
Here, if the fall of the clock signal fp output from the 1/N frequency divider is delayed compared to the fall of the reference clock signal, the 1/N frequency divider does not count the pulse of the clock signal fvco from the time of the fall of the reference clock signal. Instead, the 1/N frequency divider counts the pulse of the clock signal fvco from the time of the fall of the clock signal fp, which is later than the fall of the reference clock signal. The 1/N frequency divider then lowers the clock signal fp again. Next, the frequency of the clock signal fvco is newly determined, based on the difference of the time of the subsequent fall of the clock signal fp and the subsequent fall of the reference clock signal.
Here, the subsequent fall of the clock signal fp is related to the previous fall of the clock signal fp. Because the clock signal fp falls again after counting the pulse of the clock signal fvco N times from the time of the previous fall of the clock signal fp, the subsequent fall of the clock signal fp is related to the previous fall of the clock signal fp.
Furthermore, the clock signal fvco, which is generated based on the subsequent fall of the reference clock signal and the subsequent fall of the clock signal fp, is also related to the previous fall of the clock signal fp.
Therefore, if the previous fall of the clock signal is delayed more than the previous fall of the reference clock signal, the clock signal falls again. This fall occurs after the clock signal fvco is counted N times from the previous fall of the clock signal fp, and not from the previous fall of the reference clock signal. Thus, the subsequent fall of the reference clock signal and the subsequent fall of the clock signal fp do not match without using a clock signal fvco having an extremely high frequency. Therefore, there is a problem because it takes time to match both the frequency and phase of the reference clock signal and the clock signal fp.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a phase-locked loop circuit which overcomes the above issues in the related art.
The phase-locked loop circuit of the present invention may have: a phase comparator which compares a phase of a first frequency divided signal, generated by dividing a frequency of a reference clock signal and a phase of a second frequency divided signal, which is an output signal of a frequency dividing circuit, and outputs a signal related to the comparison; a low-pass filter which outputs a voltage related to an output signal of the phase comparator; a voltage controlled oscillator which outputs a signal having a frequency related to a voltage output from the low-pass filter; and a frequency dividing circuit which outputs a first level of the second frequency divided signal related to a reset signal generated based on the first frequency divided signal and the output signal output from the voltage controlled oscillator, and outputs a second level of the second frequency divided signal when a number of pulses of the output signal of the voltage controlled oscillator reaches a prescribed number after inputting the reset signal.
This summary of the invention does not necessarily describe all necessary features. The invention may also be a sub-combination of these described features.


REFERENCES:
patent: 5304954 (1994-04-01), Saito et al.
patent: 5389897 (1995-02-01), Gebara
patent: 6066988 (2000-05-01), Igura

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