Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

2001-08-23

2002-09-17

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C327S281000, C331S057000

Reexamination Certificate

active

06452430

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an improvement of a phase-locked loop circuit, and more particularly to an improved design of a phase-locked loop circuit for improving the operating frequency range and the stability of middle/low frequency thereof, and for adjusting accurately the frequency continuously.
BACKGROUND OF THE INVENTION
A conventional phase-locked loop circuit is shown in
FIG. 1
, in which a signal f
in
of some frequency is inputted into a divider
11
for being frequency divided by M to become a signal f
in/M
, and then inputted into a phase frequency detector
12
.
The phase frequency detector
12
will be inputted with another feedback signal f
r
having the same frequency with f
in/M
. The signal f
r
is a modified reference signal for adjusting the phase of f
in/M
. If the phase of f
in/M
is ahead of f
r
, then the phase frequency detector
12
will generate an UP signal. If the phase of f
in/M
falls behind f
r
, then the phase frequency detector
12
will generate a DN signal.
The UP signal or the DN signal will be inputted into a charge pump circuit
13
for generating a corresponding voltage V
ctrl
to be inputted into a low pass filter
14
.
The output V
o
of the low pass filter
14
will be inputted into a voltage controlled oscillator
15
for generating an oscillating signal to be inputted into a prescaler circuit
16
. After being processed by the prescaler circuit
16
, an oscillating signal f
o
will be inputted into a divider
17
for generating a required accurate frequency.
The signal f
o
is also inputted into another divider
18
for being frequency divided by N to generate the signal f
r
, and then inputted into the phase frequency detector
12
. The frequency of f
r
is the same as that of f
in/M
.
Referring to
FIG. 2
, the detailed circuit of the voltage-controlled oscillator
15
will be described. A voltage signal V
M
is inputted into the control terminals of the inverters
21
,
22
,
23
,
24
,
25
simultaneously. The inverters
21
,
22
,
23
,
24
,
25
are connected serially to form a ring, as shown in the figure. Capacitors C
1
, C
2
, C
3
, C
4
, C
5
are each parallelly connected at the output terminals a, b, c, d, e of the inverters. Therefore, oscillating signals having same frequency but different phases are each generated at the output terminals a, b, c, d, e of the inverters.
Referring to
FIG. 3
, which shows an improvement for the circuit in FIG.
2
. The improvement is that capacitors C
11
, C
12
, C
13
, capacitors C
21
, C
22
, C
23
, capacitors C
31
, C
32
, C
33
, capacitors C
41
, C
42
, C
43
, and capacitors C
51
, C
52
, C
53
are connected parallelly at the output terminals a, b, c, d, e of the inverters respectively. Signals CC
1
, CC
2
and CC
2
are used to enable switches S
11
, S
12
, S
13
, switches S
21
, S
22
, S
23
, switches S
31
, S
32
, S
33
, switches S
41
, S
42
, S
43
and switches S
51
, S
52
, S
53
that are connected serially with related capacitors respectively. By selecting signals CC
1
, CC
2
or CC
3
to turn related switches on and to enable related capacitors to become conductive, the frequency of the signals at the output terminals a, b, c, d, e can be adjusted.
Although the frequency of the signals at the output terminals a, b, c, d and e in
FIG. 3
can be adjusted, the adjustment cannot be continuous. Another disadvantage is that the sensitivity of the frequency to voltage is too high in middle/low frequency range, so it is hard to do the frequency adjustment accurately.
OBJECTS OF THE INVENTION
It is therefore an object of the present invention to provide an improved design of a voltage-controlled oscillator of a phase-locked loop circuit for improving the operating frequency range and the stability of middle/low frequency therefore, and for adjusting accurately the frequency continuously.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
shows the block diagram of a conventional phase-locked loop circuit.
FIG. 2
shows the circuit diagram of the voltage-controlled oscillator in a conventional phase-locked loop circuit.
FIG. 3
shows a prior improved circuit design of the voltage-controlled oscillator in a conventional phase-locked loop circuit.
FIG. 4
shows an improved circuit design of the voltage-controlled oscillator in a phase-locked loop circuit according to the present invention.


REFERENCES:
patent: 5828258 (1998-10-01), Ooishi et al.
patent: 5847617 (1998-12-01), Reddy et al.
patent: 6054904 (2000-04-01), Katoh et al.

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