Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-11-02
2001-03-27
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000, C327S159000, C327S261000
Reexamination Certificate
active
06208182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-locked circuit.
2. Discussion of the Related Art
A phase-locked loop circuit, as illustrated in
FIG. 1
, includes a phase comparator
2
receiving an input signal IS and a feedback signal FBS, a filter
3
receiving an output signal CS from phase comparator
2
, and a voltage-controlled oscillator (VCO)
4
, which receives an output signal FS from filter
3
and provides an output signal OS of PLL
1
and controls a feedback loop to generate the feedback signal provided to phase comparator
2
. The feedback loop can be, for example, a frequency divider
5
receiving output signal OS and generating feedback signal FBS.
An application of PLLs is in the implementation of low jitter oscillators for providing clock signals of accurate frequency and low jitter.
To provide such a clock signal, a quartz crystal oscillator is conventionally used. To generate a clock signal of given frequency, a quartz crystal oscillator, the natural frequency of which corresponds to the desired frequency, can be used. This solution is generally acceptable for frequencies up to 25 megahertz. However, obtaining higher frequencies, for example on the order of one hundred megahertz, presents problems, either because there is no quartz crystal oscillator that operates at the desired frequency, or because such a quartz crystal oscillator is expensive. It is thus generally preferred to use oscillators including an inexpensive quartz crystal of low frequency, for example, of 25 megahertz, and a frequency multiplier made from a PLL.
In practice, PLLs having a rather low jitter, for example, on the order of 150 picoseconds, can be found. A problem is that such a jitter, even though it is low, can be too high in some applications. Such is the case in high rate series links, illustrated for example in U.S. Pat. Nos. 5,268,937, 5,414,830, and 5,430,773, in which several 100-megahertz phase-shifted clock signals are used to drive the series transmission or reception at a higher frequency, for example, on the order of 1 gigahertz. It is then desired to obtain a jitter limited to a few tens of picoseconds, which is not possible with conventional PLLs.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a phase-locked loop circuit having less sensitivity to jitter.
Thus, the present invention provides a phase-locked loop circuit including a programmable ring oscillator generating drive signals; an assembly of latches receiving an input signal of the circuit, the latches being driven by the drive signals and generating samples by sampling the input signal; a logic decoding circuit receiving samples generated by latches and accordingly driving the programmable ring oscillator.
According to an embodiment, the decoding circuit includes means for comparing samples two by two to determine whether a state transition has occurred in a time interval separating the two samples, this comparison being performed over at least two cycles, consecutive or not, of the ring oscillator, so that:
if, during the second cycle, a comparable state transition is detected in the same interval, the control of the programmable ring oscillator is not modified,
if, during the second cycle, a comparable state transition is detected in a subsequent interval, a decrease of the programmable ring oscillator period is ordered,
if, during the second cycle, a comparable state transition is detected in a prior interval, an increase of the programmable ring oscillator period is ordered.
According to an embodiment, the programmable ring oscillator is formed of an assembly of programmable elements assembled in a loop, and modification of the oscillator control, when an increase or a decrease of its period is ordered, is performed on one of the programmable elements of the oscillator.
According to an embodiment, the control of the programmable ring oscillator is gradually modified, by increasing and/or decreasing its period once every M periods, with M being an integer.
According to an embodiment, the programmable ring oscillator is formed of programmable delay elements assembled in a loop.
According to an embodiment, the delay elements are non-inverting and the programmable ring oscillator includes means for modifying the state of an input signal of the first delay element, to enable oscillation of all delay elements.
According to an embodiment, the programmable ring oscillator includes multiplexing means arranged so that an input of the first delay element is connected to an output of the last element or receives a permanent logic state, the multiplexing means being controlled by a drive signal generated on an output of one of the delay elements.
According to an embodiment, the drive signals are combined in a logic adder to generate an output signal of a frequency multiple of the frequency of the programmable ring oscillator.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments made in connection with the accompanying drawings.
REFERENCES:
patent: 4244043 (1981-01-01), Fujita
patent: 5260608 (1993-11-01), Marbot
patent: 5548235 (1996-08-01), Marbot
patent: 5550515 (1996-08-01), Liang
patent: 5633899 (1997-05-01), Fiedler et al.
patent: 5684805 (1997-11-01), Brown
Lee, I., et al.: “A 622MB/S CMOS Clock Recovery PLL With Time-Interleave Phase Detector Array” IEEE International Solid State Circuits Conference, vol. 39, Feb. 1996, pp 198-199.
Couzon Guillaume
Marbot Roland
Cox Cassandra
Galanthay Theodore E.
Morris James H.
STMicroelectronics S.A.
Wells Kenneth B.
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