Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

1996-05-07

1998-10-20

Mis, David

Modulators

Frequency modulator

Including stabilization or alternatively distortion, noise...

331 18, 331 23, 331158, 331177V, H03L 706, H03B 532

Patent

active

058252584

ABSTRACT:
An improvement on the phase-locked loop (PLL) circuit, in which an amplifier is disposed at the modulating signal input end of the PLL, and the output end of the amplifier is connected in series to a resistor and an inductor, followed by a resistor connected to a higher DC bias as well as a variable capacitance diode connected to ground. In such a way, the variable capacitance diode is under the higher bias and thus has a smaller capacitance change, while having its Q-value property opposite to the resonance curve formed by the crystal unit of an oscillator which is associated in parallel with the variable capacitance diode, thereby forming in a good compensation for the linearity of the circuit architecture and achieving an ideal frequency deviation and a reduced distortion caused by the modulation.

REFERENCES:
patent: 3622913 (1971-11-01), Shipley
patent: 5423075 (1995-06-01), Boese et al.

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