Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

1980-12-24

1983-07-05

Bookbinder, Marc E.

Telecommunications

Receiver or analog modulated signal frequency converter

Signal selection based on frequency

331 1A, 455183, H04B 126, H03J 728, H03L 718

Patent

active

043922538

ABSTRACT:
A frequency synthesized receiver utilizes, as a local oscillator, a phase-locked circuit formed of a reference signal oscillator, a voltage controlled oscillator, a programmable divider, a phase comparator, and a low-pass filter. For tuning to a desired frequency, the dividing ratio of the programmable divider is controlled by an up/down counter connected in parallel with a shift register. The latter is supplied with a clock pulse signal and a binary coded selecting signal furnished from a micro computer. The selecting signal corresponds to a desired broadcast frequency. The up/down counter is caused by the micro computer to count up or down from the count value stored in the shift register, thereby causing the received frequency to rapidly sweep, at predetermined steps of, for example, 100 KHz.

REFERENCES:
patent: 3864637 (1975-02-01), Kanow
patent: 3980951 (1976-09-01), Breeze et al.
patent: 4065720 (1977-12-01), Pogue, Jr.

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