Phase-locked loop circuit

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

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331 1A, 331 8, 331 16, 331 17, 331DIG2, 327157, 327159, 455260, H03L7/089;7/095;7/18

Patent

active

059031972

ABSTRACT:
A phase-locked loop (PLL) circuit capable of attaining high-speed frequency transition with enhanced reliability. To this end, outputs of a reference signal source (1) and voltage-controlled oscillator (VCO) circuit (3) are frequency-divided by frequency divider circuits (2, 4), respectively. A phase comparator circuit (5) is provided for outputting an error signal indicative of a phase difference between these signals, if any. A window generator circuit (9) is connected for outputting a window signal; where the error signal does not fall within the range of a pulse width of this window signal, a level generator circuit generates a boost voltage having its potential near the control voltage value of the VCO (3) for use in generating of a target frequency. A low-pass filter (LPF) circuit (7) is charged up in responding to receipt of both the output signal of the charge pump circuit (6) and the boost voltage so that the control voltage may rapidly increase in potential at a target value without rising up to any excess values. Whereby, undershoot and overshoot may be eliminated or at least greatly suppressed thus enabling achievement of high-speed frequency transition with increased reliability.

REFERENCES:
patent: 4437072 (1984-03-01), Asami
patent: 4543540 (1985-09-01), Linder
patent: 4562411 (1985-12-01), O'Rourke et al.
patent: 4614917 (1986-09-01), Zelitzki
patent: 5276408 (1994-01-01), Norimatsu

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