Phase locked loop circuit

Details Phase locked loop circuit Phase locked loop circuit

1990-10-22

1991-11-12

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

331 18, 360 51, H03D 302

Patent

active

050654136

ABSTRACT:
A phase locked loop circuit is arranged such that the frequency of an input reference clock signal is selected on the basis of a first or second transmission rate of an incoming digital signal, whereby an output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate can be transmitted. Also, the phase locked loop circuit is arranged so that a first or second central frequency value and a first or second boundary frequency value are set in response to the first or second transmission rate of the incoming digital signal so that, if a frequency value of an output digital signal lies outside of a range of the first or second boundary frequency values, the frequency of the output digital signal is set to the first or second central frequency values. Thus, the phase locked loop circuit of the invention can deliver the output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate.

REFERENCES:
patent: 4375693 (1983-03-01), Kuhn
patent: 4534044 (1985-08-01), Funke et al.

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