Phase-locked loop circuit

Details Phase-locked loop circuit Phase-locked loop circuit

1995-08-30

1996-12-03

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 1A, 331 8, 331 25, 327107, 327159, H03L 300, H03L 710, H03L 716

Patent

active

055812147

ABSTRACT:
A timing generating circuit (9) receives a reference signal (f.sub.REF) and an operation control signal (S.sub.0) as inputs and outputs a generation control signal (S.sub.1). The generation control signal (S.sub.1) is inputted to the prescaler (31), the programmable divider (41) and a phase comparator (51). The generation control signal (S.sub.1) goes "H" when the operation control signal (S.sub.0) goes "H" and then the reference signal (f.sub.REF) is counted predetermined times, and a raw signal (f.sub.RAW) is divided to start generating a signal to be measured (f.sub.0) after the generation control signal (S.sub.1) goes "H", so that a phase difference .delta. between the reference signal (f.sub.REF) and the signal to be measured (f.sub.0) at the start is constant irrespective of the timing of the operation control signal (S.sub.0) attaining "H". Accordingly, it is not necessary to set the timing of the operation control signal (S.sub.0) attaining "H" considerably earlier prior to a period required in the time-division telegraphy, and the power consumption of a prescaler (31) and a programmable divider (41) are suppressed.

REFERENCES:
patent: 4105946 (1978-08-01), Ikeda
patent: 4667169 (1987-05-01), Matsuura et al.
patent: 4673892 (1987-06-01), Miyashita et al.
patent: 5113152 (1992-05-01), Norimatsu
patent: 5339278 (1994-08-01), Irwin et al.
patent: 5448195 (1995-09-01), Iga et al.
patent: 5459755 (1995-10-01), Iga et al.
patent: 5497126 (1996-03-01), Kosiec et al.

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